Datasheet > 转换器 > 模数转换器> ADC1115S125HN-C1

ADC1115S125HN-C1

更新时间： 2024-11-09 12:21:47

品牌	Logo	应用领域
艾迪悌 - IDT		转换器模数转换器双倍数据速率
页数	文件大小	规格书
36页	373K
描述
Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS DDR digital outputs

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中文翻译

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技术参数
数据手册

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ADC1115S125HN-C1 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	VFQFPN
包装说明：	6 X 6 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT618-6, HVQFN-40	针数：	40
Reach Compliance Code：	compliant	风险等级：	5.84
Is Samacsys：	N	转换器类型：	ADC, PROPRIETARY METHOD
JESD-609代码：	e3	输出位码：	OFFSET BINARY
峰值回流温度（摄氏度）：	260	端子面层：	MATTE TIN
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

ADC1115S125HN-C1 数据手册

ADC1115S125

Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS

DDR digital outputs

Rev. 03 — 2 July 2012

Product data sheet

1. General description

The ADC1115S125 is a single channel 11-bit Analog-to-Digital Converter (ADC) optimized

for high dynamic performance and low power consumption at sample rates up to

125 Msps. Pipelined architecture and output error correction ensure the ADC1115S125 is

accurate enough to guarantee zero missing codes over the entire operating range.

Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in

CMOS mode, because of a separate digital output supply.

The ADC1115S125 supports the Low Voltage Differential Signalling (LVDS) Double Data

Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the

user to easily configure the ADC.

The device also includes a SPI programmable full-scale to allow flexible input voltage

range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the

baseband to input frequencies of 170 MHz or more, the ADC1115S125 is ideal for use in

communications, imaging and medical applications - especially in high Intermediate

Frequency (IF) applications because of the integrated input buffer. The input buffer

ensures that the input impedance remains constant and low and the performance

consistent over a wide frequency range.

2. Features and benefits

 SNR, 66.5 dBFS; SFDR, 86 dBc

 Input bandwidth, 600 MHz

 Power dissipation, 840 mW including

analog input buffer

 Sample rate up to 125 Msps

 11-bit pipelined ADC core

 Clock input divided by 2 for less jitter

contribution

 Serial Peripheral Interface (SPI)

 Duty cycle stabilizer

 Integrated input buffer

 Fast OuT-of-Range (OTR) detection

 Flexible input voltage range: 1 V (p-p) to  Offset binary, two’s complement, gray

2 V (p-p)

code

 CMOS or LVDS DDR digital outputs

 Power-down mode and Sleep mode

 HVQFN40 package

 Pin compatible with the ADC1415S

series, the ADC1215S series and the

ADC1015S series

12 3 4 5 6 7...36

中文翻译

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与ADC1115S125HN-C1相关器件

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