Datasheet > ADATE207BBP

ADATE207BBP

更新时间： 2024-09-26 04:04:27

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
36页	626K
描述
Quad Pin Timing Formatter

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中文翻译

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数据手册

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ADATE207BBP 数据手册

Quad Pin Timing Formatter

ADATE207

FEATURES

FUNCTIONAL BLOCK DIAGRAM

4-channel timing formatter

256 waveforms per channel

4 independent event edges per waveform

STIL IEEE 1450-1999-compatible events

4-period range for each edge

39.06 ps timing resolution

2.5 ns minimum edge refire rate

All drive formats supported

100 MHz base vector rate

ADATE207

PATTERN

FAIL

TIME SET

MEMORY

QUAD EDGE

GENERATOR

DCL

FORMAT

COMPARE

LOGIC

INTERFACE

FAIL

DETECTION

PATTERN

FAIL

TIME SET

MEMORY

QUAD EDGE

GENERATOR

DCL

INTERFACE

FORMAT

COMPARE

LOGIC

×2 and ×4 high speed modes

×2 pin multiplexing

FAIL

DETECTION

1 ns minimum pulse width

32-bit fail counter per channel

4-bit pin capture per channel

Air cooled, low power CMOS design

6 W at 100 MHz base rate

PATTERN

FAIL

TIME SET

MEMORY

QUAD EDGE

GENERATOR

DCL

INTERFACE

FORMAT

COMPARE

LOGIC

FAIL

DETECTION

2.5 V power supply

Differential DCL interface control

TMU multiplexer

PATTERN

FAIL

TIME SET

MEMORY

QUAD EDGE

GENERATOR

DCL

INTERFACE

FORMAT

COMPARE

LOGIC

FAIL

DETECTION

APPLICATIONS

Automatic test equipment (ATE)

High speed digital instrumentation

Pulse generation

Figure 1.

generators use a reference master clock of 100 MHz and provide

programmable delays based upon counts of the clock and a

compensated CMOS analog timing vernier. The programmable

delay generators can be additionally delayed by a global 8-bit

input value that is shared across all edges.

GENERAL DESCRIPTION

The ADATE207 is a timing generator and formatter for auto-

matic test equipment (ATE) equipment. The ADATE207 provides

four independent channels with a 100 MHz base vector rate of

timing and formatting for ATE digital pins. It interfaces between

the pattern memory,and the driver, comparator, and load (DCL)

chips for complete digital pins. The ADATE207 accepts up to

eight bits of pattern data per pin and can produce formatted

outputs and perform comparisons of DUT expected responses.

The format and compare logic support ×2 pin multiplexing to

allow the trading of pin count for speed.

Each channel provides a 4-bit DUT output capture supporting

mixed signal receive memory applications. The fail detection

logic includes a 32-bit fail accumulation register per channel.

Each channel of the ADATE207 provides 256 selectable wave-

forms, wherein each waveform consists of up to four possible

events. Each event consists of a programmable timing edge and a

STIL-compatible (IEEE Standard 1450-1999) set.

An external TMU is supported with three 8-to-1 multiplexers.

This allows the dual comparator outputs of any pin to be

multiplexed to any of the three outputs: arm, start, or stop

signals.

Each timing edge generator can produce an edge with a span of

four periods with a 39.06 ps edge placement resolution. The delay

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

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与ADATE207BBP相关器件

型号	品牌	获取价格	描述	数据表
ADATE207BBPZ	ADI	获取价格	Quad Pin Timing Formatter
ADATE209	ADI	获取价格	4.0 Gbps Dual Driver
ADATE209BBCZ	ADI	获取价格	4.0 Gbps Dual Driver
ADATE302-02	ADI	获取价格	500 MHz Dual Integrated DCL with Differential Drive/Receive, Level Setting DACs, and Per P
ADATE302-02_17	ADI	获取价格	500 MHz Dual Integrated DCL
ADATE302-02BBCZ	ADI	获取价格	500 MHz Dual Integrated DCL with Differential Drive/Receive, Level Setting DACs, and Per P
ADATE302-02BSVZ	ADI	获取价格	500 MHz Dual Integrated DCL
ADATE304	ADI	获取价格	200 MHz Dual Integrated DCL with Level Setting DACs, Per Pin PMU, and Per Chip VHH
ADATE304BBCZ	ADI	获取价格	200 MHz Dual Integrated DCL with Level Setting DACs, Per Pin PMU, and Per Chip VHH
ADATE305	ADI	获取价格	250 MHz Dual Integrated DCL with Level Setting DACs, Per Pin PMU, and Per Chip VHH

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