Datasheet > ADAU1328BSTZ-RL

ADAU1328BSTZ-RL

更新时间： 2024-01-17 22:28:00

品牌	Logo	应用领域
亚德诺 - ADI		解码器编解码器
页数	文件大小	规格书
32页	395K
描述
2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec

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ADAU1328BSTZ-RL 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP,	针数：	48
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.07
模拟集成电路 - 其他类型：	ANALOG CIRCUIT	JESD-30 代码：	S-PQFP-G48
JESD-609代码：	e3	长度：	7 mm
湿度敏感等级：	3	功能数量：	1
端子数量：	48	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	7 mm	Base Number Matches：	1

ADAU1328BSTZ-RL 数据手册

2 ADC/8 DAC with PLL,

192 kHz, 24-Bit Codec

ADAU1328

FEATURES

GENERAL DESCRIPTION

PLL generated or direct master clock

Low EMI design

108 dB DAC/107 dB ADC dynamic range and SNR

−94 dB THD + N

The ADAU1328 is a high performance, single-chip codec that

provides two analog-to-digital converters (ADCs) with differential

input and eight digital-to-analog converters (DACs) with

single-ended output using the Analog Devices, Inc. patented

multibit sigma-delta (Σ-Δ) architecture. An SPI port is included,

allowing a microcontroller to adjust volume and many other

parameters. The ADAU1328 operates from 3.3 V digital and

analog supplies. The ADAU1328 is available in a 48-lead

(single-ended output) LQFP. Other members of this family

include a differential DAC output and I²C® control port version.

Single 3.3 V supply

Tolerance for 5 V logic inputs

Supports 24 bits and 8 kHz to 192 kHz sample rates

Differential ADC input

Single-ended DAC output

Log volume control with autoramp function

SPI® controllable for flexibility

Software controllable clickless mute

Software power-down

Right justified, left justified, I²S and TDM modes

Master and slave modes up to 16-channel in/out

48-lead LQFP

The ADAU1328 is designed for low EMI. This consideration is

apparent in both the system and circuit design architectures.

By using the on-board PLL to derive the master clock from the

LR clock or from an external crystal, the ADAU1328 eliminates

the need for a separate high frequency master clock and can

also be used with a suppressed bit clock. The digital-to-analog

and analog-to-digital converters are designed using the latest

ADI continuous time architectures to further minimize EMI. By

using 3.3 V supplies, power consumption is minimized, further

reducing emissions.

APPLICATIONS

Home theater systems

Set-top boxes

Digital audio effects processors

FUNCTIONAL BLOCK DIAGRAM

DIGITAL AUDIO

INPUT/OUTPUT

ADAU1328

SERIAL DATA PORT

DAC

SDATA

OUT

SDATA

DIGITAL

FILTER

AND

VOLUME

CONTROL

ADC

CLOCKS

DEC

FILTER

48/96/

TIMING MANAGEMENT

AND CONTROL

(CLOCK AND PLL)

192kHz

CONTROL

PORT

SPI/I C

PRECISION

VOLTAGE

REFERENCE

12.488MHz

6.144MHz

CONTROL DATA

INPUT/OUTPUT

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

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