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ADAU1381

更新时间: 2024-09-28 06:36:15
品牌 Logo 应用领域
亚德诺 - ADI 解码器编解码器
页数 文件大小 规格书
84页 857K
描述
Low Noise Stereo Codec with Enhanced Recording and Playback Processing

ADAU1381 数据手册

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Low Noise Stereo Codec with Enhanced  
Recording and Playback Processing  
ADAU1381  
FEATURES  
GENERAL DESCRIPTION  
24-bit stereo audio ADC and DAC  
The ADAU1381 is a low power, 24-bit stereo audio codec. The  
low noise DAC and ADC support sample rates from 8 kHz to  
96 kHz. Low current draw and power saving modes make the  
ADAU1381 ideal for battery-powered audio applications.  
400 mW speaker amplifier (into 8 Ω load)  
Built-in sound engine for audio processing  
Wind noise detection and autofiltering  
Enhanced stereo capture (ESC)  
A configurable sound engine provides enhanced record and  
playback processing to improve overall audio quality.  
Dual-band automatic level control (ALC)  
6-band equalizer, including notch filter  
Sampling rates from 8 kHz to 96 kHz  
Stereo pseudo differential microphone input  
Optional stereo digital microphone input pulse-density  
modulation (PDM)  
Stereo line output  
PLL supporting a range of input clock rates  
Analog and digital I/O 1.8 V to 3.3 V  
Software control via SigmaStudio graphical user interface  
Software-controllable, clickless mute  
Software register and hardware pin standby mode  
32-lead, 5 mm × 5 mm LFCSP or 30-ball, 6 × 5 bump WLCSP  
The record path includes two digital stereo microphone inputs  
and an analog stereo input path. The analog inputs can be  
configured for either a pseudo differential or a single-ended  
stereo source. A dedicated analog beep input signal can be  
mixed into any output path. The ADAU1381 includes a stereo  
line output and speaker driver, which makes the device capable of  
supporting dynamic speakers.  
The serial control bus supports the I2C® or SPI protocols, and  
the serial audio bus is programmable for I2S, left-justified, right-  
justified, or TDM mode. A programmable PLL supports flexible  
clock generation for all standard rates and available master clocks  
from 11 MHz to 20 MHz.  
APPLICATIONS  
Digital still cameras  
Digital video cameras  
FUNCTIONAL BLOCK DIAGRAM  
ADAU1381  
REGULATOR  
BEEP  
PGA  
SOUND ENGINE  
AOUTL  
AOUTR  
LMIC/LMICN/  
MICD1  
DECIMATION  
FILTERS  
LEFT  
LEFT  
PGA  
ADC  
DAC  
WIND NOISE  
NOTCH FILTER  
EQUALIZER  
LMICP  
OUTPUT  
MIXER  
RMIC/RMICN/  
MICD2  
SPP  
SPN  
DIGITAL VOLUME  
CONTROL  
RIGHT  
RIGHT  
DAC  
PGA  
ADC  
RMICP  
PDN  
AUTOMATIC LEVEL  
CONTROL  
2
SERIAL DATA  
INPUT/OUTPUT PORTS  
I C/SPI  
CONTROL PORT  
MICROPHONE  
BIAS  
MICBIAS  
PLL  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2009 Analog Devices, Inc. All rights reserved.  
 

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