AD9886
PCB LAYOUT RECOMMENDATIONS
phase and frequency. This can be avoided by careful attention
to regulation, filtering, and bypassing. It is highly desirable to
provide separate regulated supplies for each of the analog cir-
cuitry groups (VD and PVD).
The AD9886 is a high-precision, high-speed analog device. As
such, to get the maximum performance out of the part it is
important to have a well laid-out board. The following is a guide
for designing a board using the AD9886.
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog
supply regulator, which can in turn produce changes in the
regulated analog supply voltage. This can be mitigated by regu-
lating the analog supply, or at least PVD, from a different, cleaner
power source (for example, from a 12 V supply).
Analog Interface Inputs
Using the following layout techniques on the graphics inputs is
extremely important:
Minimize the trace length running into the graphics inputs. This
is accomplished by placing the AD9886 as close as possible to
the graphics VGA connector. Long input trace lengths are unde-
sirable because they will pick up more noise from the board and
other external sources.
It is also recommend to use a single ground plane for the entire
board. Experience has repeatedly shown that the noise perfor-
mance is the same or better with a single ground plane. Using
multiple ground planes can be detrimental because each sepa-
rate ground plane is smaller, and long ground loops can result.
Place the 75 Ω termination resistors as close to the AD9886
chip as possible. Any additional trace length between the termi-
nation resistors and the input of the AD9886 increases the
magnitude of reflections, which will corrupt the graphics signal.
In some cases, using separate ground planes is unavoidable. For
those cases, it is recommend to at least place a single ground
plane under the AD9886. The location of the split should be at
the receiver of the digital outputs. For this case it is even more
important to place components wisely because the current loops
will be much longer (current takes the path of least resistance).
An example of a current loop: power plane => AD9886 =>
digital output trace => digital data receiver => digital ground
plane => analog ground plane.
Use 75 Ω matched impedance traces. Trace impedances other
than 75 Ω will also increase the chance of reflections.
The AD9886 has very high input bandwidth (330 MHz). While
this is desirable for acquiring a high resolution PC graphics
signal with fast edges, it means that it will also capture any high
frequency noise present. Therefore, it is important to reduce the
amount of noise that gets coupled to the inputs. Avoid running
any digital traces near the analog inputs.
Due to the high bandwidth of the AD9886, sometimes low-pass
filtering the analog inputs can help to reduce noise. (For many
applications, filtering is unnecessary.) Experiments have shown
that placing a series ferrite bead prior to the 75 Ω termination
resistor is helpful in filtering out excess noise. Specifically, the
part used was the # 2508051217Z0 from Fair-Rite, but each
application may work best with a different bead value. Alternately,
placing a 100 Ω to 120 Ω resistor between the 75 Ω termination
resistor and the input coupling capacitor can also benefit.
PLL
Place the PLL loop filter components as close to the FILT pin
as possible.
Do not place any digital or other high frequency traces near
these components.
Use the values suggested in the data sheet with 10% tolerances
or less.
Outputs (Both Data and Clocks)
Digital Interface Inputs
Try to minimize the trace length that the digital outputs have to
drive. Longer traces have higher capacitance, which require
more current that causes more internal digital noise.
Many of the same techniques that are recommended for the
analog interface inputs should also be used for the digital inter-
face inputs. Most important is to minimize trace lengths, and
then to make the input traces impedances match the input ter-
mination (typically 50 Ω).
Shorter traces reduce the possibility of reflections.
Adding a series resistor of value 50 Ω–200 Ω can suppress reflec-
tions, reduce EMI, and reduce the current spikes inside of the
AD9886. If series resistors are used, place them as close to the
AD9886 pins as possible (try not to add vias or extra length to
the output trace in order to get the resistors closer).
Power Supply Bypassing
It is recommended to bypass each power supply pin with a
0.1 µF capacitor. The exception is in the case where two or
more supply pins are adjacent to each other. For these group-
ings of powers/grounds, it is only necessary to have one bypass
capacitor. The fundamental idea is to have a bypass capacitor
within about 0.5 cm of each power pin. Also, avoid placing the
capacitor on the opposite side of the PC board from the AD9886,
as that interposes resistive vias in the path.
If possible, limit the capacitance that each of the digital outputs
drives to less than 10 pF. This can easily be accomplished by
keeping traces short and by connecting the outputs to only one
device. Loading the outputs with excessive capacitance will
increase the current transients inside of the AD9886 creating
more digital noise on its power supplies.
The bypass capacitors should be physically located between the
power plane and the power pin. Current should flow from the
power plane => capacitor => power pin. Do not make the power
connection between the capacitor and the power pin. Placing a
via underneath the capacitor pads, down to the power plane, is
generally the best approach.
Digital Inputs
The digital inputs on the AD9886 were designed to work with
3.3 V signals.
Any noise that gets onto the Hsync input trace will add jitter to
the system. Therefore, minimize the trace length and do not run
any digital or other high frequency traces near it.
It is particularly important to maintain low noise and good
stability of PVD (the clock generator supply). Abrupt changes in
PVD can result in similarly abrupt changes in sampling clock
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