Dual Interface for
Flat Panel Display
AD9887A
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Analog interface
ANALOG INTERFACE
REFIN
REF
REFOUT
170 MSPS maximum conversion rate
Programmable analog bandwidth
0.5 V to 1.0 V analog input range
500 ps p-p PLL clock jitter at 170 MSPS
3.3 V power supply
R
R
8
8
OUTA
8
8
8
CLAMP
CLAMP
CLAMP
R
A/D
A/D
A/D
AIN
OUTB
G
8
8
OUTA
G
G
AIN
OUTB
B
8
8
OUTA
Full sync processing
B
AIN
Midscale clamping
4:2:2 output format mode
Digital interface
DVI 1.0-compatible interface
170 MHz operation (2 pixels/clock mode)
High skew tolerance of 1 full input clock
Sync detect for hot plugging
Supports high bandwidth digital content protection
2
DATACK
HSOUT
HSYNC
VSYNC
COAST
CLAMP
CKINV
CKEXT
FILT
SYNC
VSOUT
PROCESSING
AND CLOCK
GENERATION
8
8
SOGOUT
RED A
RED B
S
CDT
SOGIN
8
8
8
8
2
GREEN A
GREEN B
BLUE A
BLUE B
DATACK
HSOUT
VSOUT
SOGOUT
DE
SCL
SDA
A1
SERIAL REGISTER
AND
POWER MANAGEMENT
A0
APPLICATIONS
DIGITAL INTERFACE
8
R
8
8
OUTA
RGB graphics processing
LCD monitors and projectors
Plasma display panels
Scan converters
Microdisplays
Digital TVs
Rx0+
Rx0–
R
OUTB
G
8
8
OUTA
Rx1+
Rx1–
Rx2+
8
G
OUTB
B
8
8
OUTA
Rx2–
8
B
OUTB
RxC+
RxC–
RTERM
DVI
RECEIVER
2
DATACK
DE
HSOUT
VSOUT
GENERAL DESCRIPTION
DDCSCL
DDCSDA
MCL
The AD9887A offers an analog interface receiver and a digital
visual interface (DVI) receiver integrated on a single chip,
supports high bandwidth digital content protection (HDCP),
and is software and pin-to-pin compatible with the AD9887.
HDCP
MDA
AD9887A
Figure 1.
Analog Interface
Digital Interface
The complete 8-bit, 170 MSPS, monolithic analog interface is
optimized for capturing RGB graphics signals from personal
computers and workstations. Its 170 MSPS encode rate capability
and full-power analog bandwidth of 330 MHz support resolutions
of up to 1600 × 1200 (UXGA) at 60 Hz. The interface includes
a 170 MHz triple ADC with internal 1.25 V reference; a phase-
locked loop (PLL); and programmable gain, offset, and clamp
controls. The user provides only a 3.3 V power supply, analog
input, and Hsync. Three-state CMOS outputs can be powered
from 2.5 V to 3.3 V. The analog interface also offers full sync
processing for composite sync and sync-on-green (SOG) appli-
cations. The AD9887A on-chip PLL generates a pixel clock from
Hsync with output frequencies ranging from 12 MHz to 170 MHz.
PLL clock jitter is typically 500 ps p-p at 170 MSPS.
The AD9887A contains a DVI 1.0-compatible receiver and
supports resolutions up to 1600 × 1200 (UXGA) at 60 Hz. The
receiver operates with true color (24-bit) panels in one or two
pixel(s) per clock mode and features an intrapair skew tolerance
of up to one full clock cycle. With the inclusion of HDCP,
displays can receive encrypted video content. The AD9887A
allows for authentication of a video receiver, decryption of encoded
data at the receiver, and renewability of authentication during
transmission, as specified by the HDCP v1.0 protocol. Fabricated
in an advanced CMOS process, the AD9887A is provided in a
160-lead, surface-mount, plastic MQFP and is specified over the
0°C to 70°C temperature range. The AD9887A is also available
in an RoHS compliant package.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved.
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