Datasheet > AD9852ASTZ1

AD9852ASTZ1

更新时间： 2022-04-19 00:51:41

品牌	Logo	应用领域
亚德诺 - ADI		数据分配系统
页数	文件大小	规格书
52页	1382K
描述
CMOS 300 MSPS Complete DDS

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AD9852ASTZ1 数据手册

AD9852

ABSOLUTE MAXIMUM RATINGS

Table 2.

To determine the junction temperature on the application PCB

use the following equation:

Parameter

Rating

T_J= T_case+ (Ψ_JT× PD)

Maximum Junction Temperature

V_S

Digital Inputs

Digital Output Current

Storage Temperature

Operating Temperature

Lead Temperature (Soldering, 10 sec)

Maximum Clock Frequency (ASVZ)

Maximum Clock Frequency (ASTZ)

150°C

4 V

where:

−0.7 V to +V_S

5 mA

−65°C to +150°C

−40°C to +85°C

300°C

T_Jis the junction temperature expressed in degrees Celsius.

_caseis the case temperature expressed in degrees Celsius, as

measured by the user at the top center of the package.

Ψ_JT= 0.3°C/W.

PD is the power dissipation (PD); see the Power Dissipation and

Thermal Considerations section for the method to calculate PD.

300 MHz

200 MHz

EXPLANATION OF TEST LEVELS

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 4.

Test Level

Description

III

100% production tested.

Sample tested only.

Parameter is guaranteed by design and

characterization testing.

Parameter is a typical value only.

Devices are 100% production tested at 25°C and

guaranteed by design and characterization testing

for industrial operating temperature range.

THERMAL RESISTANCE

The heat sink of the AD9852ASVZ 80-lead TQFP package must

be soldered to the PCB.

ESD CAUTION

Table 3.

Thermal Characteristic

θ_JA(0 m/sec airflow)^{1, 2, 3}

θ_JMA(1.0 m/sec airflow)^{2, 3, 4, 5}

θ_JMA(2.5 m/sec airflow)^{2, 3, 4, 5}

TQFP

LQFP

16.2°C/W

13.7°C/W

12.8°C/W

0.3°C/W

2.0°C/W

38°C/W

1, 2

Ψ_JT

6, 7

θ_JC

¹Per JEDEC JESD51-2 (heat sink soldered to PCB).

²2S2P JEDEC test board.

³Values of θ_JAare provided for package comparison and PCB design

considerations.

⁴Per JEDEC JESD51-6 (heat sink soldered to PCB).

⁵Airflow increases heat dissipation, effectively reducing θ_JA. Furthermore, the

more metal that is directly in contact with the package leads from metal

traces through holes, ground, and power planes, the more θ_JAis reduced.

⁶Per MIL-Std 883, Method 1012.1.

⁷Values of θ_JCare provided for package comparison and PCB design

considerations when an external heat sink is required.

Rev. E | Page 8 of 52

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