AD9852
Test
AD9852ASVZ
AD9852ASTZ
Parameter
Temp
Level Min
Typ
Max
Min
Typ
Max
Unit
Residual Phase Noise
(AOUT = 5 MHz, External Clock = 30 MHz,
REFCLK Multiplier Engaged at 10×)
1 kHz Offset
10 kHz Offset
100 kHz Offset
25°C
25°C
25°C
V
V
V
140
138
142
140
138
142
dBc/Hz
dBc/Hz
dBc/Hz
(AOUT = 5 MHz, External Clock = 300 MHz,
REFCLK Multiplier Bypassed)
1 kHz Offset
0 kHz Offset
100 kHz Offset
25°C
25°C
25°C
V
V
V
142
148
152
142
148
152
dBc/Hz
dBc/Hz
dBc/Hz
PIPELINE DELAYS3, 4, 5
DDS Core (Phase Accumulator and
Phase-to-Amp Converter)
25°C
IV
33
33
SYSCLK cycles
Frequency Accumulator
Inverse Sinc Filter
Digital Multiplier
25°C
25°C
25°C
25°C
25°C
25°C
25°C
IV
IV
IV
IV
IV
IV
26
16
9
1
2
26
16
9
1
2
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
DAC
I/O Update Clock (Internal Mode)
I/O Update Clock (External Mode)
MASTER RESET DURATION
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance
Input Resistance
Input Current
Hysteresis
3
3
IV
10
10
25°C
25°C
25°C
25°C
V
IV
I
3
500
1
3
500
1
pF
kΩ
μA
mV p-p
5
20
5
20
IV
10
10
COMPARATOR OUTPUT CHARACTERISTICS
Logic 1 Voltage, High-Z Load
Logic 0 Voltage, High-Z Load
Output Power, 50 Ω Load, 120 MHzToggle Rate
Propagation Delay
Output Duty Cycle Error6
Rise/Fall Time, 5 pF Load
Toggle Rate, High-Z Load
Toggle Rate, 50 Ω Load
Output Cycle-to-Cycle Jitter7
COMPARATOR NARROW-BAND SFDR8
10 MHz ( 1 MHz)
10 MHz ( 250 MHz)
10 MHz ( 50 kHz)
41 MHz ( 1 MHz)
41 MHz ( 250 kHz)
41 MHz ( 50 kHz)
119 MHz ( 1 MHz)
119 MHz ( 250 kHz)
119 MHz ( 50 kHz)
Full
Full
VI
VI
I
IV
I
3.1
9
3.1
9
V
V
dBm
ns
%
0.16
+10
0.16
+10
25°C
25°C
25°C
25°C
25°C
25°C
25°C
11
3
1
2
350
400
11
3
1
2
350
400
−10
−10
V
ns
IV
IV
IV
300
375
300
375
MHz
MHz
ps rms
4.0
4.0
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
V
V
V
V
V
V
V
V
V
84
84
92
76
82
89
73
73
83
84
84
92
76
82
89
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
CLOCK GENERATOR OUTPUT JITTER8
5 MHz AOUT
40 MHz AOUT
100 MHz AOUT
25°C
25°C
25°C
V
V
V
23
12
7
23
12
7
ps rms
ps rms
ps rms
Rev. E | Page 6 of 52