AD9852
GENERAL DESCRIPTION
The AD9852 programmable 4× to 20× REFCLK multiplier cir-
cuit internally generates the 300 MHz system clock from a lower
frequency external reference clock. This saves the user the expense
and difficulty of implementing a 300 MHz system clock source.
The AD9852 digital synthesizer is a highly integrated device
that uses advanced DDS technology, coupled with an internal
high speed, high performance D/A converter to form a digitally
programmable, agile synthesizer function. When referenced to
an accurate clock source, the AD9852 generates a highly stable
frequency-, phase-, and amplitude-programmable cosine output
that can be used as an agile LO in communications, radar, and
many other applications. The innovative high speed DDS core
of the AD9852 provides 48-bit frequency resolution (1 μHz
tuning resolution with 300 MHz SYSCLK). Maintaining 17 bits
ensures excellent SFDR.
Direct 300 MHz clocking is also accommodated with either single-
ended or differential inputs. Single-pin, conventional FSK and the
enhanced spectral qualities of ramped FSK are supported. The
AD9852 uses advanced 0.35 ꢀ CMOS technology to provide this
high level of functionality on a single 3.3 V supply.
The AD9852 is pin-for-pin compatible with the AD9854 single-
tone synthesizer. The AD9852 is specified to operate over the
extended industrial temperature range of −40°C to +85°C.
The circuit architecture of the AD9852 allows the generation of
output signals at frequencies up to 150 MHz, which can be
digitally tuned at a rate of up to 100 million new frequencies
per second. The (externally filtered) cosine wave output can be
converted to a square wave by the internal comparator for agile
clock generator applications. The device provides two 14-bit
phase registers and a single pin for BPSK operation.
OVERVIEW
The AD9852 digital synthesizer is a highly flexible device that
addresses a wide range of applications. The device consists of
an NCO with a 48-bit phase accumulator, a programmable
reference clock multiplier, an inverse sinc filter, a digital
multiplier, two 12-bit/300 MHz DACs, a high speed analog
comparator, and an interface logic. This highly integrated
device can be configured to serve as a synthesized LO agile
clock generator and FSK/BPSK modulator. The theory of
operation for the functional blocks of the device and a technical
description of the signal flow through a DDS device is provided
by Analog Devices, Inc., in the tutorial A Technical Tutorial on
Digital Signal Synthesis. The tutorial also provides basic
applications information for a variety of digital synthesis
implementations.
For higher-order PSK operation, the I/O interface can be used
for phase changes. The 12-bit cosine DAC, coupled with the
innovative DDS architecture, provides excellent wideband and
narrow-band output SFDR. When configured with the
comparator, the 12-bit control DAC facilitates static duty cycle
control in the high speed clock generator applications.
The 12-bit digital multiplier permits programmable amplitude
modulation, on/off output shaped keying, and precise amplitude
control of the cosine DAC output. Chirp functionality is also
included for wide bandwidth frequency sweeping applications.
Rev. E | Page 4 of 52
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