AD9814
APPLICATIONS INFORMATION
Circuit and Layout Recommendations
should occur coincident with or before the rising edge of
ADCCLK (see Figures 1 through 4 for timing). All 0.1 µF
decoupling capacitors should be located as close as possible to
the AD9814 pins. When operating in single channel mode, the
unused analog inputs should be grounded.
The recommended circuit configuration for 3-Channel CDS
mode operation is shown in Figure 15. The recommended input
coupling capacitor value is 0.1 µF (see Circuit Operation section
for more details). A single ground plane is recommended for the
AD9814. A separate power supply may be used for DRVDD,
the digital driver supply, but this supply pin should still be
decoupled to the same ground plane as the rest of the AD9814.
The loading of the digital outputs should be minimized, either
by using short traces to the digital ASIC, or by using external
digital buffers. To minimize the effect of digital transients during
major output code transitions, the falling edge of CDSCLK2
Figure 16 shows the recommended circuit configuration for 3-
Channel SHA mode. All of the above considerations also apply
for this configuration, except that the analog input signals are
directly connected to the AD9814 without the use of coupling
capacitors. The analog input signals must already be dc-biased
between 0 V and 4 V (see the Circuit Operation section for
more details).
0.1F
+5V
RED INPUT
3
CLOCK INPUTS
0.1F
0.1F
GREEN INPUT
1
28
AVDD
CDSCLK1
CDSCLK2
ADCCLK
OEB
2
3
0.1F
27
26
25
24
23
22
21
20
19
18
AVSS
VINR
BLUE INPUT
+5V/3V
4
OFFSET
VING
DRVDD AD9814
5
0.1F
0.1F
1.0F
0.1F
0.1F
6
DRVSS
CML
7
D7 (MSB)
VINB
+
8
D6
D5
D4
D3
D2
CAPT
CAPB
AVSS
AVDD
0.1F
0.1F
10F
0.1F
9
10
11
12
SLOAD 17
SCLK
+5V
13 D1
14
16
SDATA 15
D0 (LSB)
8
3
SERIAL INTERFACE
DATA OUTPUTS
Figure 15. Recommended Circuit Configuration, 3-Channel CDS Mode
+5V
RED INPUT
3
CLOCK INPUTS
0.1F
GREEN INPUT
1
2
CDSCLK1
CDSCLK2
ADCCLK
OEB
AVDD 28
27
26
25
24
23
22
21
20
19
18
AVSS
VINR
BLUE INPUT
3
+5V/3V
4
OFFSET
VING
DRVDD AD9814
5
0.1F
0.1F
6
DRVSS
CML
0.1F
7
D7 (MSB)
VINB
+
8
D6
D5
D4
D3
D2
CAPT
CAPB
AVSS
AVDD
0.1F
0.1F
10F
0.1F
9
10
11
12
SLOAD 17
SCLK
+5V
13 D1
14
16
SDATA 15
D0 (LSB)
8
3
SERIAL INTERFACE
DATA OUTPUTS
Figure 16. Recommended Circuit Configuration, 3-Channel SHA Mode
(Analog Inputs Sampled with Respect to Ground)
–14–
REV. 0