AD9814KR

更新时间： 2024-01-05 21:00:05

品牌	Logo	应用领域
亚德诺 - ADI		模拟IC 信号电路光电二极管
页数	文件大小	规格书
15页	163K
描述
Complete 14-Bit CCD/CIS Signal Processor

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技术参数
数据手册

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AD9814KR 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP,	针数：	28
Reach Compliance Code：	unknown	风险等级：	5.63
模拟集成电路 - 其他类型：	ANALOG CIRCUIT	JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e0	长度：	17.9 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	28	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	240
认证状态：	COMMERCIAL	座面最大高度：	2.65 mm
最大供电电压 (Vsup)：	5.25 V	最小供电电压 (Vsup)：	4.75 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	7.5 mm
Base Number Matches：	1

AD9814KR 数据手册

AD9814

CIRCUIT OPERATION

Analog Inputs—CDS Mode

2. Linearity. Some of the input capacitance of a CMOS IC is

junction capacitance, which varies nonlinearly with applied

voltage. If the input coupling capacitor is too small, then the

attenuation of the CCD signal will vary nonlinearly with signal

level. This will degrade the system linearity performance.

Figure 8 shows the analog input configuration for the CDS

mode of operation. Figure 9 shows the internal timing for the

sampling switches. The CCD reference level is sampled when

CDSCLK1 transitions from high to low, opening S1. The CCD

data level is sampled when CDSCLK2 transitions from high to

low, opening S2. S3 is then closed, generating a differential

output voltage representing the difference between the two sampled

levels.

3. Sampling Errors. The internal 4 pF sample capacitors have

a “memory” of the previously sampled pixel. There is a

charge redistribution error between C_INand the internal

sample capacitors for larger pixel-to-pixel voltage swings. As

the value of C_INis reduced, the resulting error in the sampled

voltage will increase. With a C_INvalue of 0.1 µF, the charge

redistribution error will be less than 1 LSB for a full-scale

pixel-to-pixel voltage swing.

The input clamp is controlled by CDSCLK1. When CDSCLK1

is high, S4 closes and the internal bias voltage is connected to

the analog input. The bias voltage charges the external 0.1 µF

input capacitor, level-shifting the CCD signal into the AD9814’s

input common-mode range. The time constant of the input

clamp is determined by the internal 5 kΩ resistance and the

external 0.1 µF input capacitance.

Analog Inputs—SHA Mode

Figure 10 shows the analog input configuration for the SHA

mode of operation. Figure 11 shows the internal timing for the

sampling switches. The input signal is sampled when CDSCLK2

transitions from high to low, opening S1. The voltage on the

OFFSET pin is also sampled on the falling edge of CDSCLK2,

when S2 opens. S3 is then closed, generating a differential out-

put voltage representing the difference between the sampled

input voltage and the OFFSET voltage. The input clamp is

disabled during SHA mode operation.

AD9814

4pF

VINR

CCD SIGNAL

CML

0.1␮F

5k⍀

4pF

AVDD

AD9814

4pF

1.7k⍀

2.2k⍀

6.9k⍀

VINR

CML

RED

CML

INPUT SIGNAL

OFFSET

INPUT CLAMP LEVEL

IS SELECTED IN THE

CONFIGURATION

0.1␮F

1␮F

OFFSET

VING

OPTIONAL DC OFFSET

(OR CONNECT TO GND)

GREEN

BLUE

Figure 8. CDS-Mode Input Configuration (All Three Chan-

nels Are Identical)

VINB

S1, S4 CLOSED

CDSCLK1

CDSCLK2

S1, S4 OPEN

S2 CLOSED

Figure 10. SHA-Mode Input Configuration (All Three

Channels Are Identical)

S2 OPEN

S3 CLOSED

(INTERNAL)

S3 OPEN

S1, S2 CLOSED

S1, S2 OPEN

S1, S2 CLOSED

CDSCLK2

Figure 9. CDS-Mode Internal Switch Timing

S3 CLOSED

External Input Coupling Capacitors

The recommended value for the input coupling capacitors is

0.1 µF. While it is possible to use a smaller capacitor, this larger

value is chosen for several reasons:

S3 OPEN

(INTERNAL)

1. Signal Attenuation. The input coupling capacitor creates a

capacitive divider with a CMOS integrated circuit’s input

capacitance, attenuating the CCD signal level. C_INshould be

large relative to the IC’s 10 pF input capacitance in order to

minimize this effect.

Figure 11. SHA-Mode Internal Switch Timing

–12–

REV. 0

1...9 10 111213 14 15

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AD9814KRRL	ADI	IC SPECIALTY ANALOG CIRCUIT, PDSO28, 0.300 INCH, SOIC-28, Analog IC:Other	获取价格
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