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AD9822JRRL PDF预览

AD9822JRRL

更新时间: 2024-11-06 12:33:15
品牌 Logo 应用领域
亚德诺 - ADI 商用集成电路光电二极管
页数 文件大小 规格书
20页 474K
描述
Complete 14-Bit CCD/CIS Signal Processor

AD9822JRRL 数据手册

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Complete 14-Bit  
CCD/CIS Signal Processor  
AD9822  
GENERAL DESCRIPTION  
FEATURES  
14-bit 15 MSPS ADC  
The AD9822 is a complete analog signal processor for CCD  
imaging applications. It features a 3-channel architecture designed  
to sample and condition the outputs of trilinear color CCD  
arrays. Each channel consists of an input clamp, correlated double  
sampler (CDS), offset DAC, and programmable gain amplifier  
(PGA) multiplexed to a high performance 14-bit ADC.  
No missing codes guaranteed  
3-channel operation up to 15 MSPS  
1-channel operation up to 12.5 MSPS  
Correlated double sampling  
1–6× programmable gain  
350 mV programmable offset  
Input clamp circuitry  
Internal voltage reference  
Multiplexed byte-wide output (8 + 6 format)  
3-wire serial digital interface  
3 V/5 V digital I/O compatibility  
28-Lead SOIC or SSOP  
Low power CMOS: 385 mW (typ)  
Power-down mode: <1 mW  
The CDS amplifiers may be disabled for use with sensors such  
as contact image sensors (CIS) and CMOS active pixel sensors,  
which do not require CDS.  
The 14-bit digital output is multiplexed into an 8-bit output  
word that is accessed using two read cycles. The internal  
registers are programmed through a 3-wire serial interface and  
provide adjustment of the gain, offset, and operating mode.  
The AD9822 operates from a single 5 V power supply,  
consumes 385 mW of power typically, and is packaged in a  
28-lead SOIC or SSOP.  
APPLICATIONS  
Flatbed document scanners  
Film scanners  
Digital color copiers  
Multifunction peripherals  
FUNCTIONAL BLOCK DIAGRAM  
AVDD  
AVSS  
CDS  
CML  
CAPT  
CAPB  
AVDD  
AVSS  
DRVDD  
DRVSS  
AD9822  
VINR  
VING  
PGA  
OEB  
BAND GAP  
REFERENCE  
9-BIT  
DAC  
14  
8
14:8  
MUX  
14-BIT  
ADC  
3:1  
MUX  
DOUT  
CDS  
CDS  
PGA  
PGA  
9-BIT  
DAC  
CONFIGURATION  
REGISTER  
MUX  
REGISTER  
SCLK  
VINB  
DIGITAL  
RED  
GREEN  
BLUE  
CONTROL  
INTERFACE  
SLOAD  
SDATA  
6
9
9-BIT  
DAC  
GAIN  
REGISTERS  
INPUT  
CLAMP  
BIAS  
RED  
GREEN  
BLUE  
OFFSET  
OFFSET  
REGISTERS  
CDSCLK1 CDSCLK2  
ADCCLK  
Figure 1.  
Rev. B  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2005 Analog Devices, Inc. All rights reserved.  

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