11-/14-Bit, 2.5 GSPS,
RF Digital-to-Analog Converters
AD9737A/AD9739A
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Direct RF synthesis at 2.5 GSPS update rate
DC to 1.25 GHz in baseband mode
1.25 GHz to 3.0 GHz in mix-mode
Industry leading single/multicarrier IF or RF synthesis
Dual-port LVDS data interface
Up to 1.25 GSPS operation
Source synchronous DDR clocking
Pin compatible with the AD9739
RESET
IRQ
AD9737A/AD9739A
SDIO
SDO
CS
1.2V
SPI
DAC BIAS
SCLK
VREF
I120
Programmable output current: 8.7 mA to 31.7 mA
Low power: 1.1 W at 2.5 GSPS
IOUTN
IOUTP
TxDAC
CORE
APPLICATIONS
DCI
Broadband communications systems
DOCSIS CMTS systems
Military jammers
Instrumentation, automatic test equipment
Radar, avionics
CLK DISTRIBUTIONꢀ
DLL
(DIV-BY-4)
(MU CONTROLLER)
DCO
DACCLK
Figure 1.
GENERAL DESCRIPTION
The AD9737A/AD9739A are 11-bit and 14-bit, 2.5 GSPS high
performance RF DACs that are capable of synthesizing wideband
signals from dc up to 3 GHz. The AD9737A/AD9739A are pin
and functionally compatible with the AD9739 with the
exception that the AD9737A/AD9739A do not support
synchronization or RZ mode, and are specified to operate
between 1.6 GSPS and 2.5 GSPS.
The AD9737A/AD9739A are manufactured on a 0.18 µm
CMOS process and operate from 1.8 V and 3.3 V supplies.
They are supplied in a 160-ball chip scale ball grid array for
reduced package parasitics.
PRODUCT HIGHLIGHTS
1. Ability to synthesize high quality wideband signals with
bandwidths of up to 1.25 GHz in the first or second
Nyquist zone.
2. A proprietary quad-switch DAC architecture provides
exceptional ac linearity performance while enabling mix-
mode operation.
3. A dual-port, double data rate, LVDS interface supports the
maximum conversion rate of 2500 MSPS.
4. On-chip controllers manage external and internal clock
domain skews.
By elimination of the synchronization circuitry, some nonideal
artifacts such as images and discrete clock spurs remain stationary
on the AD9737A/AD9739A between power-up cycles, thus
allowing for possible system calibration. AC linearity and noise
performance remain the same between the AD9739 and the
AD9737A/AD9739A.
The inclusion of on-chip controllers simplifies system integration.
A dual-port, source synchronous, LVDS interface simplifies the
digital interface with existing FGPA/ASIC technology. On-chip
controllers are used to manage external and internal clock domain
variations over temperature to ensure reliable data transfer from
the host to the DAC core. A serial peripheral interface (SPI) is
used for device configuration as well as readback of status
registers.
5. Programmable differential current output with an 8.66 mA
to 31.66 mA range.
Rev.C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011-2012 Analog Devices, Inc. All rights reserved.
5秒后页面跳转
英伟达新AI芯片Rubin或提前半年亮相
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
三星深化印度制造布局，供应链本地化进程加速
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
