8-, 10-, 12-, 14-Bit, 175 MSPS
TxDAC® D/A Converters
Preliminary Technical Data
AD9704/AD9705/AD9706/AD9707
FEATURES1
0
FUNCTIONAL BLOCK DIAGRAMS
Pin-compatible Family
Low Power Member of Pin Compatible
TxDAC Product Family
Power Dissipation @ 3.3 V:
21 mW @ 10 MSPS
24 mW @ 25 MSPS
30 mW @ 50 MSPS
Sleep Mode: 5 mW @ 3.3 V
Supply Voltage: 1.7 V to 3.6 V
SFDR to Nyquist:
AD9707: 85 dBc @ 5 MHz Output
AD9707: 80 dBc @ 10 MHz Output
AD9707: 75 dBc @ 20 MHz Output
AD9707 SNR @ 10 MHz Output, 125 MSPS: TBD dB
Differential Current Outputs: 1 mA to 5 mA
Data Format: Twos Complement or Straight Binary
On-Chip 1.0 V Reference
Figure 1. AD9707 Functional Block Diagram (LFCSP Package)
CMOS Compatible Digital Interface
Edge-Triggered Latches
32-LEAD LFCSP PACKAGE FEATURES
Clock Input: Single-Ended and Differential
Output Common Mode: Adjustable 0 V to 1.2 V
Power-Down Mode: < 400 μW @ 3.3 V (SPI Controllable)
Serial Peripheral Interface (SPI)
Figure 2. AD9707 Functional Block Diagram (TSSOP Package)
Self-calibration
32-Lead LFCSP Pb-Free Package
28-LEAD TSSOP PACKAGE FEATURES
Internal 500Ω Load Resistor
Internal 16kΩ Resistor to Set Full Scale Current Output
Clock Input: Single-Ended
28-Lead TSSOP Pb-Free Package
1 Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519
Rev. PrC
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