8-Bit, 125 MSPS, Dual TxDAC+
Digital-to-Analog Converter
AD9709
FEATURES
FUNCTIONAL BLOCK DIAGRAM
DVDD1/ DCOM1/
DVDD2 DCOM2 AVDD ACOM
8-bit dual transmit digital-to-analog converter (DAC)
125 MSPS update rate
Excellent SFDR to Nyquist @ 5 MHz output: 66 dBc
Excellent gain and offset matching: 0.1%
Fully independent or single-resistor gain control
Dual port or interleaved data
CLK1
I
I
OUTA1
OUTB1
1
1
DAC
PORT1
LATCH
REFIO
FSADJ1
FSADJ2
GAINCTRL
REFERENCE
WRT1/IQWRT
WRT2/IQSEL
DIGITAL
AD9709
INTERFACE
On-chip 1.2 V reference
BIAS
GENERATOR
SLEEP
Single 5 V or 3.3 V supply operation
Power dissipation: 380 mW @ 5 V
Power-down mode: 50 mW @ 5 V
48-lead LQFP
I
OUTA2
2
2
DAC
PORT2
LATCH
I
OUTB2
MODE
CLK2/IQ RESET
Figure 1.
APPLICATIONS
Communications
Base stations
Digital synthesis
Quadrature modulation
3D ultrasound
glitch energy and to maximize dynamic accuracy. Each DAC
provides differential current output, thus supporting single-
ended or differential applications. Both DACs can be
simultaneously updated and provide a nominal full-scale
current of 20 mA. The full-scale currents between each DAC
are matched to within 0.1%.
GENERAL DESCRIPTION
The AD97091 is a dual-port, high speed, 2-channel, 8-bit CMOS
DAC. It integrates two high quality 8-bit TxDAC+® cores, a voltage
reference, and digital interface circuitry into a small 48-lead LQFP
package. The AD9709 offers exceptional ac and dc performance
while supporting update rates of up to 125 MSPS.
The AD9709 is manufactured on an advanced low-cost CMOS
process. It operates from a single supply of 3.3 V or 5 V and
consumes 380 mW of power.
The AD9709 has been optimized for processing I and Q data in
communications applications. The digital interface consists of two
double-buffered latches as well as control logic. Separate write
inputs allow data to be written to the two DAC ports independent
of one another. Separate clocks control the update rate of the DACs.
PRODUCT HIGHLIGHTS
1. The AD9709 is a member of a pin-compatible family of
dual TxDACs providing 8-, 10-, 12-, and 14-bit resolution.
2. Dual 8-Bit, 125 MSPS DACs. A pair of high performance
DACs optimized for low distortion performance provide
for flexible transmission of I and Q information.
A mode control pin allows the AD9709 to interface to two separate
data ports, or to a single interleaved high speed data port. In inter-
leaving mode, the input data stream is demuxed into its original
I and Q data and then latched. The I and Q data is then converted
by the two DACs and updated at half the input data rate.
3. Matching. Gain matching is typically 0.1% of full scale, and
offset error is better than 0.02%.
The GAINCTRL pin allows two modes for setting the full-scale
current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set
independently using two external resistors, or IOUTFS for both
DACs can be set by using a single external resistor. See the Gain
Control Mode section for important date code information on
this feature.
4. Low Power. Complete CMOS dual DAC function operates
at 380 mW from a 3.3 V or 5 V single supply. The DAC
full-scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.
5. On-Chip Voltage Reference. The AD9709 includes a 1.20 V
temperature-compensated band gap voltage reference.
6. Dual 8-Bit Inputs. The AD9709 features a flexible dual-
port interface, allowing dual or interleaved input data.
The DACs utilize a segmented current source architecture
combined with a proprietary switching technique to reduce
1 Patent pending.
Rev. B
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