Datasheet > AD9680_17

AD9680_17

更新时间： 2022-02-26 09:14:31

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
99页	3113K
描述
Dual Analog-to-Digital Converter

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AD9680_17 数据手册

Data Sheet

AD9680

SPECIFICATIONS

DC SPECIFICATIONS

AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified

maximum sampling rate for each speed grade, A_IN= −1.0 dBFS, clock divider = 2, default SPI settings, T_A= 25°C, unless otherwise noted.

Table 1.

AD9680-500

AD9680-820

AD9680-1000

AD9680-1250

Parameter

Temp Min Typ Max Min Typ

Max Min

Typ

Max

Min

Typ

Max

Unit

RESOLUTION

ACCURACY

Full

Bits

No Missing Codes

Offset Error

Offset Matching

Gain Error

Gain Matching

Differential Nonlinearity

(DNL)

Integral Nonlinearity (INL)

TEMPERATURE DRIFT

Offset Error

Full

Guaranteed

−0.3

+0.3 −0.3

0.3

5.1

+0.3 −0.31

0.23

5.5

+0.31 −0.31

0.23

+0.31 % FSR

0.3

4.5

% FSR

LSB

−6

4.5

−6

−0.6

−4.5

0.5 +0.7 −0.7

0.5 +0.8 −0.7

0.5

2.5

+0.8

−0.8

−6

0.5 +0.8

Full

2.5 +5.0 −3.3

2.5 +4.3 −5.7

+6.9

LSB

Full

−3

−10

−12

13.8

−15

ppm/°C

Gain Error

INTERNAL VOLTAGE

REFERENCE

Voltage

Full

1.0

INPUT-REFERRED NOISE

V_REF= 1.0 V

25°C

2.06

2.46

2.63

3.45

LSB rms

ANALOG INPUTS

Differential Input Voltage

Range (Programmable)

Common-Mode Voltage

(V_CM)

Differential Input

Capacitance¹

Analog Input Full Power

Bandwidth

Full

1.46 2.06 2.06 1.46 1.70 1.94 1.46

1.70

2.05

1.5

1.94

1.46

1.58

2.05

1.5

1.94

V p-p

25°C

2.05

1.5

2.05

1.5

GHz

POWER SUPPLY

AVDD1

AVDD2

AVDD3

AVDD1_SR

DVDD

DRVDD

SPIVDD

I_AVDD1

Full

25°C

Full

1.22 1.25 1.28 1.22 1.25 1.28 1.22

2.44 2.50 2.56 2.44 2.50 2.56 2.44

1.25

2.50

3.3

1.25

1.8

685

595

125

208

200

N/A³

1.28

2.56

3.4

1.28

3.4

720

680

142

269

225

1.22

2.44

3.2

1.22

1.7

1.25

2.50

3.3

1.25

1.8

785

675

125

250

220

N/A³

1.28

2.56

3.4

1.28

3.4

880

780

142

325

300

3.2

3.3

3.4

3.2

3.3

3.4

3.2

1.22 1.25 1.28 1.22 1.25 1.28 1.22

1.7

1.8

3.4

1.7

1.8

3.4

1.7

435 467

395 463

605

490

125

660

545

140

I_AVDD2

I_AVDD3

101

I_{AVDD1_SR}

I_DVDD

145 152

190 237

140

205

200

N/A³

246

240

I_DRVDD

I_DRVDD(L = 2 Mode)

I_SPIVDD

Rev. C | Page 5 of 97

1...4 5 678 9 10...99

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