Datasheet > AD9680-LF500EBZ

AD9680-LF500EBZ

更新时间： 2024-11-05 00:47:31

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
99页	3113K
描述
Dual Analog-to-Digital Converter

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数据手册

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AD9680-LF500EBZ 数据手册

14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS

JESD204B, Dual Analog-to-Digital Converter

Data Sheet

AD9680

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD

SPIVDD

JESD204B (Subclass 1) coded serial digital outputs

1.65 W total power per channel at 1 GSPS (default settings)

SFDR at 1 GSPS = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz

SNR at 1 GSPS = 65.3 dBFS at 340 MHz (A_IN= −1.0 dBFS),

60.5 dBFS at 1 GHz (A_IN= −1.0 dBFS)

ENOB = 10.8 bits at 10 MHz

(1.25V) (2.5V) (3.3V)

(1.25V)

(1.25V) (1.25V) (1.8V TO 3.3V)

BUFFER

VIN+A

VIN–A

ADC

CORE

DDC

FD_A

SERDOUT0±

SIGNAL

MONITOR

SERDOUT1±

SERDOUT2±

SERDOUT3±

DNL = 0.5 LSB

FD_B

DDC

INL = 2.5 LSB

VIN+B

VIN–B

ADC

CORE

Noise density = −154 dBFS/Hz at 1 GSPS

1.25 V, 2.5 V, and 3.3 V dc supply operation

No missing codes

BUFFER

CONTROL

REGISTERS

V_1P0

FAST

DETECT

Internal ADC voltage reference

Flexible input range: 1.46 V p-p to 1.94 V p-p

AD9680-1250: 1.58 V p-p nominal

SIGNAL

MONITOR

SYNCINB±

SYSREF±

JESD204B

SUBCLASS 1

CONTROL

CLOCK

GENERATION

AD9680-1000 and AD9680-820: 1.70 V p-p nominal

AD9680-500: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)

Programmable termination impedance

400 Ω, 200 Ω, 100 Ω, and 50 Ω differential

2 GHz usable analog input full power bandwidth

95 dB channel isolation/crosstalk

CLK+

CLK–

÷2

÷4

÷8

SPI CONTROL

PDWN/

STBY

AD9680

AGND DRGND DGND SDIO SCLK CSB

Figure 1.

Amplitude detect bits for efficient AGC implementation

2 integrated wideband digital processors per channel

12-bit NCO, up to 4 half-band filters

Differential clock input

Integer clock divide by 1, 2, 4, or 8

Flexible JESD204B lane configurations

Small signal dither

PRODUCT HIGHLIGHTS

1. Wide full power bandwidth supports IF sampling of signals

up to 2 GHz.

2. Buffered inputs with programmable input termination eases

filter design and implementation.

3. Four integrated wideband decimation filters and numerically

controlled oscillator (NCO) blocks supporting multiband

receivers.

APPLICATIONS

4. Flexible serial port interface (SPI) controls various product

features and functions to meet specific system requirements.

5. Programmable fast overrange detection.

6. 9 mm × 9 mm, 64-lead LFCSP.

Communications

Diversity multiband, multimode digital receivers

3G/4G, TD-SCDMA, W-CDMA, GSM, LTE

General-purpose software radios

Ultrawideband satellite receivers

Instrumentation

Radars

Signals intelligence (SIGINT)

DOCSIS 3.0 CMTS upstream receive paths

HFC digital reverse path receivers

Rev. C

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

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与AD9680-LF500EBZ相关器件

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AD9683	ADI	获取价格	14-Bit, 170 MSPS/250 MSPS, JESD204B, Analog-to-Digital Converter
AD9683-170EBZ	ADI	获取价格	14-Bit, 170 MSPS/250 MSPS, JESD204B, Analog-to-Digital Converter
AD9683-250EBZ	ADI	获取价格	14-Bit, 170 MSPS/250 MSPS, JESD204B, Analog-to-Digital Converter
AD9683BCPZ-170	ADI	获取价格	14-Bit, 170 MSPS/250 MSPS, JESD204B, Analog-to-Digital Converter
AD9683BCPZ-250	ADI	获取价格	14-Bit, 170 MSPS/250 MSPS, JESD204B, Analog-to-Digital Converter

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