14-Bit, 170 MSPS/250 MSPS, JESD204B,
Analog-to-Digital Converter
Data Sheet
AD9683
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD DRVDD DVDD
AGND DGND DRGND
JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and
250 MSPS
Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz AIN
and 250 MSPS
Total power consumption: 434 mW at 250 MSPS
1.8 V supply voltages
Integer 1-to-8 input clock divider
AD9683
JESD204B
INTERFACE
VIN+
VIN–
VCM
CML, TX
PIPELINE
14-BIT ADC
SERDOUT0±
OUTPUTS
HIGH
SPEED
SERIALIZERS
CMOS
DIGITAL
INPUT
CONTROL
REGISTERS
PDWN
Sample rates of up to 250 MSPS
SYSREF±
SYNCINB±
CLK±
IF sampling frequencies of up to 400 MHz
Internal analog-to-digital converter (ADC) voltage reference
Flexible analog input range
CLOCK
GENERATION
RFCLK
CMOS
DIGITAL
OUTPUT
FAST
DETECT
CMOS DIGITAL
INPUT/OUTPUT
FD
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer (DCS)
Serial port control
SDIO SCLK CS
RST
Energy saving power-down modes
Figure 1.
GENERAL DESCRIPTION
APPLICATIONS
The AD9683 is a 14-bit ADC with sampling speeds of up to
250 MSPS. The AD9683 is designed to support communications
applications where low cost, small size, wide bandwidth, and
versatility are desired.
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
Smart antenna systems
Electronic test and measurement equipment
Radar receivers
COMSEC radio architectures
IED detection/jamming systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC core features wide bandwidth inputs supporting a variety
of user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer (DCS) is
provided to compensate for variations in the ADC clock duty cycle,
allowing the converter to maintain excellent performance. The
JESD204B high speed serial interface reduces board routing
requirements and lowers pin count requirements for the
receiving device.
The ADC output data is routed directly to the JESD204B serial
output lane. These outputs are at CML voltage levels. Data can be
sent through the lane at the maximum sampling rate of 250 MSPS,
which results in a lane rate of 5 Gbps. Synchronization inputs
(SYNCINB and SYSREF ) are provided.
Rev. 0
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
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Tel: 781.329.4700
Technical Support
©2013 Analog Devices, Inc. All rights reserved.
www.analog.com
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