AD9680
Data Sheet
APPLICATIONS INFORMATION
plane must have several vias to achieve the lowest possible
POWER SUPPLY RECOMMENDATIONS
resistive thermal path for heat dissipation to flow through the
bottom of the PCB. These vias must be solder filled or plugged.
The number of vias and the fill determine the resulting θJA
measured on the board.
The AD9680 must be powered by the following seven supplies:
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR =
1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, and SPIVDD = 1.80 V.
For applications requiring an optimal high power efficiency and
low noise performance, it is recommended that the ADP2164
and ADP2370 switching regulators be used to convert the 3.3 V,
5.0 V, or 12 V input rails to an intermediate rail (1.8 V and 3.8 V).
These intermediate rails are then postregulated by very low
noise, low dropout (LDO) regulators (ADP1741, ADM7172,
and ADP125). Figure 174 shows the recommended power
supply scheme for the AD9680.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This
provides several tie points between the ADC and PCB during
the reflow process, whereas using one continuous plane with no
partitions only guarantees one tie point. See Figure 175 for a
PCB layout example. For detailed information on packaging
and the PCB layout of chip scale packages, see the AN-772
Application Note, A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP).
AVDD1
1.25V
ADP1741
1.8V
AVDD1_SR
1.25V
DVDD
1.25V
ADP1741
ADP125
DRVDD
1.25V
SPIVDD
(1.8V OR 3.3V)
3.6V
3.3V
AVDD3
3.3V
ADM7172
OR
AVDD2
2.5V
ADP1741
Figure 174. High Efficiency, Low Noise Power Solution for the AD9680
It is not necessary to split all of these power domains in all cases.
The recommended solution shown in Figure 174 provides the
lowest noise, highest efficiency power delivery system for the
AD9680. If only one 1.25 V supply is available, route to AVDD1
first and then tap it off and isolate it with a ferrite bead or a filter
choke, preceded by decoupling capacitors for AVDD1_SR, DVDD,
and DRVDD, in that order. This is shown as the optional path
in Figure 174. The user can employ several different decoupling
capacitors to cover both high and low frequencies. These capacitors
must be located close to the point of entry at the PCB level and
close to the devices, with minimal trace lengths.
Figure 175. Recommended PCB Layout of Exposed Pad for the AD9680
AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60)
AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) can be
used to provide a separate power supply node to the SYSREF
circuits of AD9680. If running in Subclass 1, the AD9680 can
support periodic one-shot or gapped signals. To minimize the
coupling of this supply into the AVDD1 supply node, adequate
supply bypassing is needed.
EXPOSED PAD THERMAL HEAT SLUG
RECOMMENDATIONS
The exposed pad on the underside of the ADC must be connected
to AGND to achieve the best electrical and thermal performance
of the AD9680. Connect an exposed continuous copper plane
on the PCB to the AD9680 exposed pad, Pin 0. The copper
Rev. C | Page 96 of 97
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