Datasheet > AD9680-500EBZ

AD9680-500EBZ

更新时间： 2022-02-26 09:14:31

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
99页	3113K
描述
Dual Analog-to-Digital Converter

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数据手册

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AD9680-500EBZ 数据手册

AD9680

Data Sheet

Reg

Addr

(Hex)

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB) Default

Notes

0x564

Output

channel

select

Converter

channel

swap

0x00

0 =

normal

channel

ordering

1 =

channel

swap

enabled

0x00 for

AD9680-

1250,

AD9680-

1000 and

AD9680-

820;

0x10 for

AD9680-

500

0x56E

JESD204B

lane rate

control

0 = serial

lane rate

≥6.25 Gbps

and

≤12.5 Gbps

1 = serial

lane rate

must be ≥

3.125 Gbps

and

≤6.25 Gbps

0x56F

0x570

JESD204B

PLL lock

status

PLL lock

0 = not

locked

0x00

Read

only

1 = locked

JESD204B

quick config-

uration

JESD204B quick configuration

L = number of lanes = 2^{Register 0x570, Bits[7:6]}

M = number of converters = 2^{Register 0x570, Bits[5:3]}

F = number of octets/frame = 2 ^{Register 0x570, Bits[2:0]}

0x88 for

AD9680-

1250,

Refer to

Table 26

and

AD9680- Table 27

1000 and

AD9680-

820;

0x49 for

AD9680-

500

Long

Lane synch-

ronization

0 = disable

FACI uses

/K28.7/

1 = enable

FACI uses

/K28.3/ and

/K28.7/

ILAS sequence mode

00 = ILAS disabled

01 = ILAS enabled

11 = ILAS always on test

mode

FACI

0 =

enabled

1 =

disabled

Link

0x14

0x571

JESD204B

Link Mode

Control 1

Standby

mode

0 = all

converter

outputs 0

1 = CGS

(/K28.5/)

Tail bit

(t) PN

0 =

disable

1 =

enable

T = N΄ −

N − CS

transport

layer test

0 =

disable

1 =

control

0 = active

1 = power

down

enable

SYNCINB

pin type

0 =

differential

1 = CMOS

8-bit/10-bit

bypass

0 = normal

8-/10-bit

bit invert

0 =

normal

1 = invert

the abcd

efghij

0x00

0x572

0x573

JESD204B

Link Mode

Control 2

SYNCINB pin control

00 = normal

10 = ignore SYNCINB

(force CGS)

11 = ignore SYNCINB

(force ILAS/user data)

SYNCINB

pin invert

0 = active

low

1 = active

high

1 = bypass

symbols

JESD204B

Link Mode

Control 3

CHKSUM mode

00 = sum of all 8-bit link

config registers

01 = sum of individual

link config fields

10 = checksum set to

zero

Test injection point

00 = N΄ sample input

01 = 10-bit data at

8-bit/10-bit output

(for PHY testing)

10 = 8-bit data at

scrambler input

JESD204B test mode patterns

0000 = normal operation (test mode disabled)

0001 = alternating checker board

0010 = 1/0 word toggle

0011 = 31-bit PN sequence—X³¹+ X²⁸+ 1

0100 = 23-bit PN sequence—X²³+ X¹⁸+ 1

0101 = 15-bit PN sequence—X¹⁵+ X¹⁴+ 1

0110 = 9-bit PN sequence—X⁹+ X⁵+ 1

0111 = 7-bit PN sequence—X⁷+ X⁶+ 1

1000 = ramp output

1110 = continuous/repeat user test

1111 = single user test

Rev. C | Page 92 of 97

1...91 92 939495 96 97...99

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