Quad, 16-Bit, 125 MSPS, Serial LVDS 1.8 V
Analog-to-Digital Converter
Data Sheet
AD9653
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD
1.8 V supply operation
Low power: 164 mW per channel at 125 MSPS
SNR = 76.5 dBFS at 70 MHz (2.0 V p-p input span)
SNR = 77.5 dBFS at 70 MHz (2.6 V p-p input span)
SFDR = 90 dBc (to Nyquist, 2.0 V p-p input span)
DNL = 0.7 LSB; INL = 3.5 LSB (2.0 V p-p input span)
Serial LVDS (ANSI-644, default) and low power, reduced
range option (similar to IEEE 1596.3)
650 MHz full power analog bandwidth
2 V p-p input voltage range (supports up to 2.6 V p-p)
Serial port control
D0+A
D0–A
SERIAL
LVDS
16
VIN+A
VIN–A
DIGITAL
PIPELINE
ADC
SERIALIZER
D1+A
D1–A
SERIAL
LVDS
16
VIN+B
DIGITAL
SERIALIZER
PIPELINE
ADC
D0+B
D0–B
SERIAL
LVDS
VIN–B
RBIAS
VREF
SERIAL
LVDS
D1+B
D1–B
SENSE
FCO+
FCO–
D0+C
D0–C
D1+C
D1–C
1V
AD9653
REF
SELECT
SERIAL
LVDS
AGND
16
16
VIN+C
VIN–C
DIGITAL
SERIALIZER
PIPELINE
ADC
SERIAL
LVDS
D0+D
D0–D
SERIAL
LVDS
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Multichip sync and clock divider
VIN+D
VIN–D
DIGITAL
SERIALIZER
PIPELINE
ADC
D1+D
D1–D
DCO+
DCO–
SERIAL
LVDS
SERIAL PORT
INTERFACE
CLOCK
MANAGEMENT
VCM
Programmable output clock and data alignment
Standby mode
APPLICATIONS
Medical ultrasound and MRI
High speed imaging
Figure 1.
Quadrature radio receivers
Diversity radio receivers
Test equipment
as programmable output clock and data alignment and digital
test pattern generation. The available digital test patterns
include built-in deterministic and pseudorandom patterns, along
with custom user-defined test patterns entered via the serial port
interface (SPI).
GENERAL DESCRIPTION
The AD9653 is a quad, 16-bit, 125 MSPS analog-to-digital con-
verter (ADC) with an on-chip sample-and-hold circuit
designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 125 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The AD9653 is available in a RoHS-compliant, 48-lead LFCSP.
It is specified over the industrial temperature range of −40°C to
+85°C. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Small Footprint.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
Four ADCs are contained in a small, space-saving package.
2. Low power of 164 mW/channel at 125 MSPS with scalable
power options.
3. Pin compatible to the AD9253 14-bit quad and the AD9633
12-bit quad ADC.
4. Ease of Use.
A data clock output (DCO) operates at frequencies of up to
500 MHz and supports double data rate (DDR) operation.
5. User Flexibility.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than 2 mW
when all channels are disabled. The ADC contains several features
designed to maximize flexibility and minimize system cost, such
The SPI control offers a wide range of flexible features to
meet specific system requirements.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
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