Datasheet > AD9634

AD9634

更新时间： 2022-10-09 09:27:33

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
32页	1575K
描述
12-Bit, 170 MSPS/210 MSPS/250 MSPS

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AD9634 数据手册

AD9634

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless

otherwise noted.

Table 3.

Parameter

Temperature

Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Internal Common-Mode Bias

Differential Input Voltage

Input Voltage Range

Full

0.9

3.ꢁ

V p-p

0.3

AGND

0.9

−22

AVDD

1.ꢀ

Input Common-Mode Range

High Level Input Current

Low Level Input Current

Input Capacitance

μA

kΩ

−10

ꢀ

Input Resistance

LOGIC INPUT (CSB)¹

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.22

−5

2.1

0.ꢁ

μA

kΩ

2ꢁ

Input Capacitance

LOGIC INPUT (SCLK)²

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.22

ꢀ5

−5

2.1

0.ꢁ

μA

kΩ

2ꢁ

Input Capacitance

LOGIC INPUTS (SDIO)¹

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.22

ꢀ5

−5

2.1

0.ꢁ

μA

kΩ

2ꢁ

Input Capacitance

DIGITAL OUTPUTS

LVDS Data and OR Outputs (OR+, OR−)

Differential Output Voltage (V_OD), ANSI Mode

Output Offset Voltage (V_OS), ANSI Mode

Differential Output Voltage (V_OD), Reduced Swing Mode

Output Offset Voltage (V_OS), Reduced Swing Mode

Full

250

1.15

150

1.15

350

1.25

200

1.25

ꢀ50

1.35

280

1.35

¹Pull-up.

²Pull-down.

Rev. 0 | Page ꢁ of 32

1...3 4 567 8 9...32

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