Datasheet > AD9576BCPZ

AD9576BCPZ

更新时间： 2024-01-18 08:13:17

品牌	Logo	应用领域
亚德诺 - ADI		时钟外围集成电路晶体
页数	文件大小	规格书
65页	1002K
描述
Dual PLL, Asynchronous Clock Generator

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技术参数
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AD9576BCPZ 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	HVQCCN,
针数：	64	Reach Compliance Code：	compliant
风险等级：	2.32	其他特性：	IT ALSO OPERATES AT 3.3V NOM SUPPLY
JESD-30 代码：	S-XQCC-N64	JESD-609代码：	e3
长度：	9 mm	湿度敏感等级：	3
端子数量：	64	最高工作温度：	85 °C
最低工作温度：	-40 °C	最大输出时钟频率：	1250 MHz
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	主时钟/晶体标称频率：	25 MHz
座面最大高度：	0.8 mm	最大供电电压：	2.625 V
最小供电电压：	2.375 V	标称供电电压：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	9 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：	1

AD9576BCPZ 数据手册

AD9576

Data Sheet

APPLICATIONS INFORMATION

INTERFACING TO CMOS CLOCK OUTPUTS

INTERFACING TO LVDS AND HSTL CLOCK

OUTPUTS

Apply the following general guidelines when using the single-

ended 1.8 V or 3.3 V CMOS clock output drivers.

LVDS and HSTL both employ a differential output driver. The

recommended termination circuit for LVDS and HSTL drivers

appears in Figure 41.

Design point to point nets such that a driver has only one

receiver on the net, if possible. This allows simple termination

schemes and minimizes ringing due to possible mismatched

impedances on the net. Series termination at the source is

generally required to provide transmission line matching and/or

to reduce current transients at the driver.

3.3V

100ꢀ

50ꢀ

10ꢀ

CMOS

5pF

The value of the series termination depends on the board

design and timing requirements (typically 10 Ω to 100 Ω).

CMOS outputs are limited in terms of the capacitive load or

trace length that they can drive. Typically, trace lengths less

than 6 inches are recommended to preserve signal rise/fall

times and signal integrity.

Figure 41. CMOS Output with Far End Termination

See the AN-586 Application Note for more information about

LVDS.

INTERFACING TO HCSL CLOCK OUTPUTS

60.4ꢀ

HCSL uses a differential open-drain architecture. The open-

drain architecture necessitates the use of an external termination

resistor. Figure 42 shows the typical method for interfacing to

HCSL drivers.

1.0 INCH

10ꢀ

CMOS

MICROSTRIP

5pF

GND

INDEPENDENT

UNCOUPLED 50ꢀ

Figure 39. Series Termination of CMOS Output

TRANSMISSION LINES

HCSL

Termination at the far end of the PCB trace is a second option.

The CMOS outputs of the AD9576 do not supply enough current

to provide a full voltage swing with a low impedance resistive,

far end termination, as shown in Figure 40. Ensure that the

impedance of the far end termination network matches the PCB

trace impedance and provides the desired switching point. The

reduced signal swing may still meet receiver input requirements

in some applications. This can be useful when driving long

trace lengths on less critical nets.

RECEIVER

50ꢀ

Figure 42. HCSL Output Termination

In some cases, the fast switching capability of HCSL drivers

results in overshoot and ringing. The alternative HCSL interface

shown in Figure 43 can mitigate this problem via a small series

resistor, typically in the 10 Ω to 30 Ω range.

INDEPENDENT

UNCOUPLED 50ꢀ

TRANSMISSION LINES

INDEPENDENT

UNCOUPLED 50ꢀ

TRANSMISSION LINES

HCSL

100ꢀ

10ꢀ TO 30ꢀ

RECEIVER

HSTL/LVDS

DRIVER

RECEIVER

50ꢀ

Figure 40. LVDS or HSTL Output Termination

Figure 43. Alternate HCSL Output Termination

Rev. 0 | Page 62 of 64

1...60 61 626364 65

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AD9576BCPZ 替代型号

型号	品牌	替代类型	描述	数据表
AD9576BCPZ	ADI	当前型号	Dual PLL, Asynchronous Clock Generator
AD9576BCPZ-REEL7	ADI	完全替代	Dual PLL, Asynchronous Clock Generator

与AD9576BCPZ相关器件

型号	品牌	获取价格	描述	数据表
AD9576BCPZ-REEL7	ADI	获取价格	Dual PLL, Asynchronous Clock Generator
AD9577	ADI	获取价格	Clock Generator with Dual PLLs
AD9577BCPZ	ADI	获取价格	Clock Generator with Dual PLLs
AD9577BCPZ-R7	ADI	获取价格	Clock Generator with Dual PLLs
AD9577BCPZ-RL	ADI	获取价格	Clock Generator with Dual PLLs
AD9577-EVALZ	ADI	获取价格	Clock Generator with Dual PLLs
AD9578	ADI	获取价格	Dual PLL Precision Synthesizer
AD9578BCPZ	ADI	获取价格	Dual PLL Precision Synthesizer
AD9578BCPZ-REEL7	ADI	获取价格	Dual PLL Precision Synthesizer
AD95S08KAC	ETC	获取价格	THYRISTOR MODULE\|DOUBLER\|HALF-CNTLD\|POSITIVE\|15V V(RRM)\|95A I(T)

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