Datasheet > AD9550BCPZ-REEL7

AD9550BCPZ-REEL7

更新时间： 2024-02-15 11:18:11

品牌	Logo	应用领域
亚德诺 - ADI		通信时钟
页数	文件大小	规格书
20页	393K
描述
Integer-N Clock Translator for Wireline Communications

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AD9550BCPZ-REEL7 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN, LCC32,.2SQ,20	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.77
应用程序：	SONET;SDH	JESD-30 代码：	S-XQCC-N32
JESD-609代码：	e3	长度：	5 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	32	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC32,.2SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	260	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	0.8 mm
子类别：	Other Telecom ICs	最大压摆率：	0.185 mA
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	5 mm	Base Number Matches：	1

AD9550BCPZ-REEL7 数据手册

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AD9550

1000

100

Output Dividers

The output divider section consists of three dividers: P₀, P₁, and P₂.

The P₀divider (or VCO frequency prescaler) accepts the VCO

frequency and reduces it by an integer factor of 5 to 11, thereby

reducing the frequency to a range between 305 MHz and 810 MHz.

AD9550

The output of the P₀divider independently drives the P₁divider

and the P₂divider. The P₁divider establishes the frequency at

OUT1 and the P₂divider establishes the frequency at OUT2.

The P₁and P₂dividers are each programmable over a range of

1 to 1023, which results in a frequency at OUT1 or OUT2 that

is an integer submultiple of the frequency at the output of the

P₀divider.

MASK

0.1

0.01

0.1

100

10M

JITTER FREQUENCY (kHz)

Output Driver Mode Control

Figure 25. Jitter Tolerance

Three mode control pins (OM0, OM1, and OM2) establish the

logic family and pin function of the output drivers. The logic

families include LVDS, LVPECL, and CMOS (see Table 10).

LOW DROPOUT (LDO) REGULATORS

The AD9550 is powered from a single 3.3 V supply and contains

on-chip LDO regulators for each function to eliminate the need

for external LDOs. To ensure optimal performance, each LDO

output should have a 0.47 μF capacitor connected between its

access pin and ground.

Table 10. Logic Family Assignment via the OMx Pins

Logic Family

Pin OMx

000

001

010

011

OUT1

LVPECL

LVDS

LVPECL

LVDS

OUT2

LVPECL

LVDS

LVPECL

CMOS

LVDS

AUTOMATIC POWER-ON RESET

The AD9550 has an internal power-on reset circuit (see Figure 26).

At power-up, an 800 pF capacitor momentarily holds a Logic 0 at

the active low input of the reset circuitry. This ensures that the

device is held in a reset state (~250 µs) until the capacitor charges

sufficiently via the 100 kΩ pull-up resistor and 200 kΩ series

resistor. Note that when using a low impedance source to drive

100

101

110

111

LVDS

CMOS

LVDS

CMOS

RESET

the

pin, be sure that the source is either tristate or Logic 0

Because both output drivers support the LVDS and LVPECL

logic families, each driver has two pins to handle the differential

signals associated with these two logic families. The OUT1 driver

at power-up; otherwise, the device may not calibrate properly.

VDD

AD9550

OUT1

uses the OUT1 and

pins, and the OUT2 driver uses the

pins. When the OMx pins select the CMOS

OUT1

100kΩ

OUT2

OUT2 and

logic family, the signal at the

of the signal at the OUT1 pin and the signal at the

200kΩ

RESET

CIRCUITRY

800pF

RESET

pin is a phase aligned replica

OUT2

pin is a

phase aligned replica of the signal at the OUT2 pin.

Figure 26. Power-On Reset

JITTER TOLERANCE

Provided an input reference signal is present at the REF pin, the

device automatically performs a VCO calibration during power-up.

If the input reference signal is not present, VCO calibration fails

and the PLL does not lock. As soon as an input reference signal

is present, the user must reset the device to initiate the automatic

VCO calibration process.

Jitter tolerance is the ability of the AD9550 to maintain lock in the

presence of sinusoidal jitter. The AD9550 meets the input jitter

tolerance mask per Telcordia GR-253-CORE (see Figure 25).

The acceptable jitter tolerance is the region above the mask.

Any change to the preset frequency selection pins requires the

user to reset the device. This is necessary to initiate the automatic

VCO calibration process.

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与AD9550BCPZ-REEL7相关器件

型号	品牌	获取价格	描述	数据表
AD9551	ADI	获取价格	Multiservice Clock Generator
AD9551/PCBZ	ADI	获取价格	Multiservice Clock Generator
AD9551BCPZ	ADI	获取价格	Multiservice Clock Generator
AD9551BCPZ-REEL7	ADI	获取价格	Multiservice Clock Generator
AD9552	ADI	获取价格	Oscillator Frequency Upconverter
AD9552BCPZ	ADI	获取价格	Oscillator Frequency Upconverter
AD9552BCPZ-REEL7	ADI	获取价格	Oscillator Frequency Upconverter
AD9552PCBZ	ADI	获取价格	Oscillator Frequency Upconverter
AD9553	ADI	获取价格	Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet
AD9553/PCBZ	ADI	获取价格	Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet

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