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AD9518-2BCPZ PDF预览

AD9518-2BCPZ

更新时间: 2024-10-28 21:14:59
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 驱动输出元件逻辑集成电路
页数 文件大小 规格书
65页 3278K
描述
9518 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC48, 7 X 7 MM, ROHS COMPLIANT, MO-220VKKD-2, LFCSP-48

AD9518-2BCPZ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:48
Reach Compliance Code:unknown风险等级:5.68
系列:9518输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-XQCC-N48JESD-609代码:e3
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:48
实输出次数:6最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
传播延迟(tpd):1.18 ns认证状态:COMMERCIAL
Same Edge Skew-Max(tskwd):0.22 ns座面最大高度:1 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mm最小 fmax:2950 MHz
Base Number Matches:1

AD9518-2BCPZ 数据手册

 浏览型号AD9518-2BCPZ的Datasheet PDF文件第6页浏览型号AD9518-2BCPZ的Datasheet PDF文件第7页浏览型号AD9518-2BCPZ的Datasheet PDF文件第8页浏览型号AD9518-2BCPZ的Datasheet PDF文件第10页浏览型号AD9518-2BCPZ的Datasheet PDF文件第11页浏览型号AD9518-2BCPZ的Datasheet PDF文件第12页 
AD9518-2  
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)  
Table 8.  
Parameter  
Min Typ Max Unit  
Test Conditions/Comments  
LVPECL OUTPUT ABSOLUTE TIME JITTER  
Application example based on a typical  
setup where the reference source is clean,  
so a wider PLL loop bandwidth is used;  
reference = 15.36 MHz; R = 1  
VCO = 2.21 GHz; LVPECL = 245.76 MHz; PLL LBW = 138 kHz  
VCO = 2.21 GHz; LVPECL = 122.88 MHz; PLL LBW = 138 kHz  
VCO = 2.21 GHz; LVPECL = 61.44 MHz; PLL LBW = 138 kHz  
146  
329  
151  
329  
203  
376  
fs rms Integration BW = 200 kHz to 10 MHz  
fs rms Integration BW = 12 kHz to 20 MHz  
fs rms Integration BW = 200 kHz to 10 MHz  
fs rms Integration BW = 12 kHz to 20 MHz  
fs rms Integration BW = 200 kHz to 10 MHz  
fs rms Integration BW = 12 kHz to 20 MHz  
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)  
Table 9.  
Parameter  
Min Typ Max Unit  
Test Conditions/Comments  
LVPECL OUTPUT ABSOLUTE TIME JITTER  
Application example based on a typical  
setup where the reference source is  
jittery, so a narrower PLL loop bandwidth  
is used; reference = 10.0 MHz; R = 20  
VCO = 2.18 GHz; LVPECL = 155.52 MHz; PLL LBW = 125 Hz  
VCO = 2.21 GHz; LVPECL = 122.88 MHz; PLL LBW = 125 Hz  
515  
570  
fs rms  
fs rms  
Integration BW = 12 kHz to 20 MHz  
Integration BW = 12 kHz to 20 MHz  
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)  
Table 10.  
Parameter  
Min Typ Max Unit  
Test Conditions/Comments  
LVPECL OUTPUT ABSOLUTE TIME JITTER  
Application example based on a typical  
setup using an  
external 245.76 MHz VCXO (Toyocom  
TCO-2112);  
reference = 15.36 MHz; R = 1  
LVPECL = 245.76 MHz; PLL LBW = 125 Hz  
LVPECL = 122.88 MHz; PLL LBW = 125 Hz  
LVPECL = 61.44 MHz; PLL LBW = 125 Hz  
54  
77  
109  
79  
114  
163  
124  
176  
259  
fs rms  
fs rms  
fs rms  
fs rms  
fs rms  
fs rms  
fs rms  
fs rms  
fs rms  
Integration BW = 200 kHz to 5 MHz  
Integration BW = 200 kHz to 10 MHz  
Integration BW = 12 kHz to 20 MHz  
Integration BW = 200 kHz to 5 MHz  
Integration BW = 200 kHz to 10 MHz  
Integration BW = 12 kHz to 20 MHz  
Integration BW = 200 kHz to 5 MHz  
Integration BW = 200 kHz to 10 MHz  
Integration BW = 12 kHz to 20 MHz  
Rev. A | Page 8 of 64  
 

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