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AD9518-2BCPZ PDF预览

AD9518-2BCPZ

更新时间： 2024-02-09 09:51:39
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 驱动输出元件逻辑集成电路
页数 文件大小 规格书
65页 3278K
描述
9518 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC48, 7 X 7 MM, ROHS COMPLIANT, MO-220VKKD-2, LFCSP-48

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AD9518-2BCPZ 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFN
包装说明：HVQCCN, LCC48,.27SQ,20针数：48
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.73
系列：9518输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-XQCC-N48JESD-609代码：e3
长度：7 mm逻辑集成电路类型：CLOCK DRIVER
湿度敏感等级：3功能数量：1
反相输出次数：端子数量：48
实输出次数：6最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC48,.27SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：1.18 ns传播延迟（tpd）：1.18 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.22 ns
座面最大高度：1 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mm最小 fmax：2950 MHz
Base Number Matches：1

AD9518-2BCPZ 数据手册

 浏览型号AD9518-2BCPZ的Datasheet PDF文件第59页浏览型号AD9518-2BCPZ的Datasheet PDF文件第60页浏览型号AD9518-2BCPZ的Datasheet PDF文件第61页浏览型号AD9518-2BCPZ的Datasheet PDF文件第63页浏览型号AD9518-2BCPZ的Datasheet PDF文件第64页浏览型号AD9518-2BCPZ的Datasheet PDF文件第65页 
AD9518-2  
VS_LVPECL  
LVPECL  
V
= 3.3V  
S
LVPECL CLOCK DISTRIBUTION  
Z
Z
= 50Ω  
= 50Ω  
0
The LVPECL outputs of the AD9518 provide the lowest jitter  
clock signals available from the AD9518. The LVPECL outputs  
(because they are open emitter) require a dc termination to bias  
the output transistors. The simplified equivalent circuit in  
Figure 42 shows the LVPECL output stage.  
50Ω  
50Ω  
50Ω  
LVPECL  
0
Figure 54. AC-Coupled LVPECL with Parallel Transmission Line  
LVPECL Y-termination is an elegant termination scheme that  
uses the fewest components and offers both odd- and even-mode  
impedance matching. Even-mode impedance matching is an  
important consideration for closely coupled transmission lines  
at high frequencies. Its main drawback is that it offers limited  
flexibility for varying the drive strength of the emitter-follower  
LVPECL driver. This can be an important consideration when  
driving long trace lengths but is usually not an issue. In the case  
where VS_LVPECL = 2.5 V, the 50 Ω termination resistor  
In most applications, a LVPECL far-end Thevenin termination  
(see Figure 52) or Y-termination (see Figure 53) is recommended.  
In both cases, VS of the receiving buffer should match the  
VS_LVPECL. If not, ac coupling is recommended (see  
Figure 54).  
VS_DRV  
VS_LVPECL  
LVPECL  
V
S
127Ω  
127Ω  
50Ω  
SINGLE-ENDED  
(NOT COUPLED)  
connected to ground in Figure 53 should be changed to 19 Ω.  
LVPECL  
Thevenin-equivalent termination uses a resistor network to provide  
50 Ω termination to a dc voltage that is below VOL of the LVPECL  
driver. In this case, VS_LVPECL on the AD9518 should equal  
VS of the receiving buffer. Although the resistor combination  
shown results in a dc bias point of VS_LVPECL − 2 V, the actual  
common-mode voltage is VS_LVPECL − 1.3 V because there is  
additional current flowing from the AD9518 LVPECL driver  
through the pull-down resistor.  
50Ω  
83Ω  
83Ω  
Figure 52. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination  
VS_LVPECL  
LVPECL  
V
= 3.3V  
S
Z
Z
= 50Ω  
= 50Ω  
0
50Ω  
50Ω  
50Ω  
The circuit is identical when VS_LVPECL = 2.5 V, except that the  
pull-down resistor is 62.5 Ω and the pull-up is 250 Ω.  
LVPECL  
0
Figure 53. DC-Coupled 3.3 V LVPECL Y-Termination  
Rev. A | Page 61 of 64  
 
 
 
 
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