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AD9518-2BCPZ

更新时间： 2024-01-30 11:11:59
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 驱动输出元件逻辑集成电路
页数 文件大小 规格书
65页 3278K
描述
9518 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC48, 7 X 7 MM, ROHS COMPLIANT, MO-220VKKD-2, LFCSP-48

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AD9518-2BCPZ 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFN
包装说明：HVQCCN, LCC48,.27SQ,20针数：48
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.73
系列：9518输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-XQCC-N48JESD-609代码：e3
长度：7 mm逻辑集成电路类型：CLOCK DRIVER
湿度敏感等级：3功能数量：1
反相输出次数：端子数量：48
实输出次数：6最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC48,.27SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：1.18 ns传播延迟（tpd）：1.18 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.22 ns
座面最大高度：1 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mm最小 fmax：2950 MHz
Base Number Matches：1

AD9518-2BCPZ 数据手册

 浏览型号AD9518-2BCPZ的Datasheet PDF文件第56页浏览型号AD9518-2BCPZ的Datasheet PDF文件第57页浏览型号AD9518-2BCPZ的Datasheet PDF文件第58页浏览型号AD9518-2BCPZ的Datasheet PDF文件第60页浏览型号AD9518-2BCPZ的Datasheet PDF文件第61页浏览型号AD9518-2BCPZ的Datasheet PDF文件第62页 
AD9518-2  
Reg.  
Addr.  
(Hex) Bits  
Name  
Description  
0x196 [7:4]  
[3:0]  
Divider 2 low cycles  
Number of clock cycles (minus 1) of the divider input during which divider output stays low.  
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).  
Divider 2 high cycles  
Divider 2 bypass  
Number of clock cycles (minus 1) of the divider input during which divider output stays high.  
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).  
0x197  
7
6
5
4
Bypasses and powers down the divider; route input to divider output.  
0: uses divider (default).  
1: bypasses divider.  
Divider 2 nosync  
Nosync.  
0: obeys chip-level SYNC signal (default).  
1: ignores chip-level SYNC signal.  
Divider 2 force high  
Divider 2 start high  
Forces divider output to high. This requires that nosync (Bit 6) also be set.  
0: divider output forced to low (default).  
1: divider output forced to high.  
Select clock output to start high or start low.  
0: starts low (default).  
1: starts high.  
[3:0]  
1
Divider 2 phase offset  
Phase offset (default = 0x0).  
0x198  
Divider 2 direct to output  
Connects OUT4 and OUT5 to Divider 2 or directly to VCO or CLK.  
0: OUT4 and OUT5 are connected to Divider 2 (default).  
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT4 and OUT5.  
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT4 and OUT5.  
If Register 0x1E1[1:0] = 01b, there is no effect.  
Duty-cycle correction function.  
0
Divider 2 DCCOFF  
0: enables duty-cycle correction (default).  
1: disables duty-cycle correction.  
Table 47. VCO Divider and CLK Input  
Reg.  
Addr  
(Hex) Bits  
Name  
Description  
0x1E0 [2:0]  
VCO divider  
2
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
Divide  
2.  
3.  
4 (default).  
5.  
6.  
Output static. Note that setting the VCO divider static should occur only  
after VCO calibration.  
1
1
1
1
0
1
Output static. Note that setting the VCO divider static should occur only  
after VCO calibration.  
Output static. Note that setting the VCO divider static should occur only  
after VCO calibration.  
0x1E1  
4
3
2
Power down clock input section  
Power down VCO clock interface  
Power down VCO and CLK  
Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).  
0: normal operation (default).  
1: power-down.  
Powers down the interface block between VCO and clock distribution.  
0: normal operation (default).  
1: power-down.  
Powers down both VCO and CLK input.  
0; normal operation (default).  
1: power-down.  
Rev. A | Page 58 of 64  
 
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