AD9516-5

更新时间： 2022-05-09 11:48:51

品牌	Logo	应用领域
亚德诺 - ADI		时钟发生器
页数	文件大小	规格书
76页	1131K
描述
14-Output Clock Generator

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数据手册

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AD9516-5 数据手册

AD9516-5

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLK = 1 GHz, Output = 50 MHz

Divider = 20

Input slew rate > 1 V/ns

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

>10 MHz Offset

−124

−134

−142

−151

−157

−160

−163

dBc/Hz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

Application example based on a typical setup using

an external 245.76 MHz VCXO (Toyocom TCO-2112);

reference = 15.36 MHz; R = 1

LVPECL = 245.76 MHz; PLL LBW = 125 Hz

LVPECL = 122.88 MHz; PLL LBW = 125 Hz

LVPECL = 61.44 MHz; PLL LBW = 125 Hz

109

114

163

124

176

259

fs rms

Integration bandwidth = 200 kHz to 5 MHz

Integration bandwidth = 200 kHz to 10 MHz

Integration bandwidth = 12 kHz to 20 MHz

Integration bandwidth = 200 kHz to 5 MHz

Integration bandwidth = 200 kHz to 10 MHz

Integration bandwidth = 12 kHz to 20 MHz

Integration bandwidth = 200 kHz to 5 MHz

Integration bandwidth = 200 kHz to 10 MHz

Integration bandwidth = 12 kHz to 20 MHz

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL;

uses rising edge of clock signal

CLK = 622.08 MHz; LVPECL = 622.08 MHz;

Divider = 1

CLK = 622.08 MHz; LVPECL = 155.52 MHz;

Divider = 4

CLK = 1.6 GHz; LVPECL = 100 MHz;

Divider = 16

CLK = 500 MHz; LVPECL = 100 MHz;

Divider = 5

fs rms

Bandwidth = 12 kHz to 20 MHz

215

245

Calculated from SNR of ADC method; DCC not used

for even divides

Calculated from SNR of ADC method; DCC on

LVDS OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL;

uses rising edge of clock signal

CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2

(VCO Divider Not Used)

fs rms

Bandwidth = 12 kHz to 20 MHz

CLK = 1 GHz; LVDS = 200 MHz; Divider = 5

CLK = 1.6 GHz; LVDS = 100 MHz; Divider = 16

113

280

fs rms

Bandwidth = 12 kHz to 20 MHz

Calculated from SNR of ADC method; DCC not used

for even divides

CMOS OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL; uses

rising edge of clock signal

CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16

365

fs rms

Calculated from SNR of ADC method; DCC not used

for even divides

Rev. A | Page 8 of 76

1...5 6 789 10 11...76

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