AD9516-5

更新时间： 2022-05-09 11:48:51

品牌	Logo	应用领域
亚德诺 - ADI		时钟发生器
页数	文件大小	规格书
76页	1131K
描述
14-Output Clock Generator

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数据手册

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AD9516-5 数据手册

AD9516-5

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

PRESCALER (PART OF N DIVIDER)

Prescaler Input Frequency

P = 1 FD

See the VCXO/VCO Feedback Divider N—P, A, B section

300

600

900

200

MHz

P = 2 FD

P = 3 FD

P = 2 DM (2/3)

P = 4 DM (4/5)

P = 8 DM (8/9)

P = 16 DM (16/17)

P = 32 DM (32/33)

Prescaler Output Frequency

1000 MHz

2400 MHz

3000 MHz

300

MHz

A, B counter input frequency (prescaler input frequency

divided by P)

PLL DIVIDER DELAYS

000

001

010

011

100

101

110

111

Off

330

440

550

660

770

880

990

NOISE CHARACTERISTICS

In-Band Phase Noise of the Charge

Pump/Phase Frequency Detector

(In-Band Is Within the LBW of the PLL)

The PLL in-band phase noise floor is estimated by

measuring the in-band phase noise at the output of

the VCO and subtracting 20 log(N) (where N is the

value of the N divider)

At 500 kHz PFD Frequency

At 1 MHz PFD Frequency

At 10 MHz PFD Frequency

At 50 MHz PFD Frequency

PLL Figure of Merit (FOM)

−165

−162

−151

−143

−220

dBc/Hz

Reference slew rate > 0.25 V/ns; FOM + 10 log(f_PFD) is

an approximation of the PFD/CP in-band phase noise

(in the flat region) inside the PLL loop bandwidth; when

running closed-loop, the phase noise, as observed at

the VCO output, is increased by 20 log(N)

PLL DIGITAL LOCK DETECT WINDOW²

Signal available at the LD, STATUS, and REFMON pins

when selected by appropriate register settings

Required to Lock (Coincidence of Edges)

Low Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 6.0 ns)

Selected by Register 0x017[1:0] and Register 0x018[4]

3.5

7.5

3.5

To Unlock After Lock (Hysteresis)²

Low Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 6.0 ns)

REFIN

The REFIN and

self-bias points are offset slightly to avoid chatter on an open input condition.

²For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.

Rev. A | Page 5 of 76

1 2 3 456 7 8...76

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