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AD9516-0BCPZ

更新时间: 2024-01-24 09:51:31
品牌 Logo 应用领域
亚德诺 - ADI 时钟驱动器时钟发生器逻辑集成电路
页数 文件大小 规格书
84页 1918K
描述
14-Output Clock Generator with Integrated 2.8 GHz VCO

AD9516-0BCPZ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:64
Reach Compliance Code:unknown风险等级:5.68
系列:9516输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-XQCC-N64JESD-609代码:e3
长度:9 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:64
实输出次数:10最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260传播延迟(tpd):2.6 ns
认证状态:COMMERCIALSame Edge Skew-Max(tskwd):0.675 ns
座面最大高度:1 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:9 mm
最小 fmax:2950 MHzBase Number Matches:1

AD9516-0BCPZ 数据手册

 浏览型号AD9516-0BCPZ的Datasheet PDF文件第75页浏览型号AD9516-0BCPZ的Datasheet PDF文件第76页浏览型号AD9516-0BCPZ的Datasheet PDF文件第77页浏览型号AD9516-0BCPZ的Datasheet PDF文件第79页浏览型号AD9516-0BCPZ的Datasheet PDF文件第80页浏览型号AD9516-0BCPZ的Datasheet PDF文件第81页 
AD9516-0  
Table 60. System  
Reg.  
Addr  
(Hex) Bit(s) Name  
Description  
230 <2> Power-Down Sync  
Power down the SYNC function.  
<2> = 0; normal operation of the SYNC function.  
<2> = 1; power-down sync circuitry.  
230 <1> Power-Down Distribution Reference Power down the reference for distribution section.  
<1> = 0; normal operation of the reference for the distribution section.  
<1> = 1; power down the reference for the distribution section.  
230 <0> Soft SYNC  
The soft SYNC bit works the same as the SYNC pin, except that the polarity of this bit  
reversed. That is, a high level forces selected channels into a predetermined static  
state, and a 1-to-0 transition triggers a sync.  
<0> = 0; same as SYNC high.  
<0> = 1; same as SYNC low.  
Table 61. Update All Registers  
Reg.  
Addr  
(Hex) Bit(s) Name  
Description  
232 <0> Update All  
Registers  
This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This happens  
on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0.  
<0> = 1 (self-clearing); update all active registers to the contents of the buffer registers.  
Rev. 0 | Page 78 of 84  
 

AD9516-0BCPZ 替代型号

型号 品牌 替代类型 描述 数据表
AD9516-0BCPZ ADI

当前型号

14-Output Clock Generator with Integrated 2.8 GHz VCO
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完全替代

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AD9516-1BCPZ-REEL7 ADI

完全替代

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