AD9516-0BCPZ

更新时间： 2024-02-22 01:36:09

品牌	Logo	应用领域
亚德诺 - ADI		时钟驱动器时钟发生器逻辑集成电路
页数	文件大小	规格书
84页	1918K
描述
14-Output Clock Generator with Integrated 2.8 GHz VCO

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技术参数
数据手册

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AD9516-0BCPZ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	64
Reach Compliance Code：	unknown	风险等级：	5.68
系列：	9516	输入调节：	DIFFERENTIAL MUX
JESD-30 代码：	S-XQCC-N64	JESD-609代码：	e3
长度：	9 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
湿度敏感等级：	3	功能数量：	1
反相输出次数：		端子数量：	64
实输出次数：	10	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出特性：	3-STATE
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	传播延迟（tpd）：	2.6 ns
认证状态：	COMMERCIAL	Same Edge Skew-Max（tskwd）：	0.675 ns
座面最大高度：	1 mm	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	9 mm
最小 fmax：	2950 MHz	Base Number Matches：	1

AD9516-0BCPZ 数据手册

AD9516-0

APPLICATION NOTES

LVPECL CLOCK DISTRIBUTION

USING THE AD9516 OUTPUTS FOR ADC CLOCK

APPLICATIONS

The LVPECL outputs of the AD9516 provide the lowest jitter

clock signals available from the AD9516. The LVPECL outputs

(because they are open emitter) require a dc termination to bias

the output transistors. The simplified equivalent circuit in

Figure 57 shows the LVPECL output stage.

Any high speed, ADC is extremely sensitive to the quality of its

sampling clock. An ADC can be thought of as a sampling mixer,

and any noise, distortion, or timing jitter on the clock is

combined with the desired signal at the analog-to-digital

output. Clock integrity requirements scale with the analog input

frequency and resolution, with higher analog input frequency

applications at ≥14-bit resolution being the most stringent. The

theoretical SNR of an ADC is limited by the ADC resolution

and the jitter on the sampling clock. Considering an ideal ADC

of infinite resolution where the step size and quantization error

can be ignored, the available SNR can be expressed

In most applications, an LVPECL far-end Thevenin termination

is recommended, as shown in Figure 69. The resistor network is

designed to match the transmission line impedance (50 Ω) and

the switching threshold (V_S− 1.3 V).

VS_LVPECL

LVPECL

127Ω

50Ω

approximately by

SINGLE-ENDED

(NOT COUPLED)

LVPECL

⎛

⎜

⎝

⎞

⎟

⎠

SNR(dB) = 20×log

2πf_At_J

50Ω

83Ω

= V – 1.3V

where:

f_Ais the highest analog frequency being digitized.

t_Jis the rms jitter on the sampling clock.

Figure 69. LVPECL Far-End Thevenin Termination

VS_LVPECL

0.1nF

Figure 68 shows the required sampling clock jitter as a function

of the analog frequency and effective number of bits (ENOB).

100Ω DIFFERENTIAL

(COUPLED)

100Ω

LVPECL

110

0.1nF

TRANSMISSION LINE

SNR = 20log

2πf_At_J

100

200Ω

Figure 70. LVPECL with Parallel Transmission Line

LVDS CLOCK DISTRIBUTION

The AD9516 provides four clock outputs (OUT6 to OUT9) that

are selectable as either CMOS or LVDS level outputs. LVDS is a

differential output option that uses a current mode output stage.

The nominal current is 3.5 mA, which yields 350 mV output

swing across a 100 Ω resistor. The LVDS output meets or

exceeds all ANSI/TIA/EIA-644 specifications.

100

A recommended termination circuit for the LVDS outputs is

shown in Figure 71.

f_A(MHz)

Figure 68. SNR and ENOB vs. Analog Input Frequency

See AN-756 and AN-501 application notes at www.analog.com.

Many high performance ADCs feature differential clock inputs

to simplify the task of providing the required low jitter clock on

a noisy PCB. (Distributing a single-ended clock on a noisy PCB

can result in coupled noise on the sample clock. Differential

distribution has inherent common-mode rejection that can

provide superior clock performance in a noisy environment.)

The AD9516 features both LVPECL and LVDS outputs that

provide differential clock outputs, which enable clock solutions

that maximize converter SNR performance. The input

requirements of the ADC (differential or single-ended, logic

level, termination) should be considered when selecting the best

clocking/converter solution.

100Ω

LVDS

DIFFERENTIAL (COUPLED)

Figure 71. LVDS Output Termination

See AN-586 application note at www.analog.com for more

information on LVDS.

Rev. 0 | Page 79 of 84

1...76 77 787980 81 82...84

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