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AD9411/PCB PDF预览

AD9411/PCB

更新时间: 2024-10-28 02:53:11
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
28页 1216K
描述
10-Bit, 170/200 MSPS 3.3 V A/D Converter

AD9411/PCB 数据手册

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10-Bit, 170/200 MSPS  
3.3 V A/D Converter  
AD9411  
FEATURES  
SNR = 60 dB @ fIN up to 70 MHz @ 200 MSPS  
ENOB of 9.8 @ fIN up to 70 MHz @ 200 MSPS (–0.5 dBFS)  
SFDR = 80 dBc @ fIN up to 70 MHz @ 200 MSPS (–0.5 dBFS)  
Excellent linearity:  
FUNCTIONAL BLOCK DIAGRAM  
SENSE VREF AGND DRGND DRVDD AVDD  
SCALABLE  
REFERENCE  
DNL = 0.15 LSB (typical)  
AD9411  
INL = 0.25 LSB (typical)  
LVDS output levels  
700 MHz full-power analog bandwidth  
On-chip reference and track-and-hold  
Power dissipation = 1.25 W typical @ 200 MSPS  
1.5 V input voltage range  
DATA,  
OVERRANGE  
IN LVDS  
ADC  
10-BIT  
PIPELINE  
CORE  
VIN+  
VIN–  
10  
/
TRACK  
AND  
HOLD  
LVDS  
OUTPUTS  
3.3 V supply operation  
Output data format option  
CLK+  
CLK–  
Clock duty cycle stabilizer  
Pin compatible to LVDS mode AD9430  
CLOCK  
MANAGEMENT  
LVDS TIMING  
DCO+  
DCO–  
S1  
S5  
APPLICATIONS  
Wireless and wired broadband communications  
Cable reverse path  
Figure 1.  
Communications test equipment  
Radar and satellite subsystems  
Power amplifier linearization  
GENERAL DESCRIPTION  
PRODUCT HIGHLIGHTS  
The AD9411 is a 10-bit monolithic sampling analog-to-digital  
converter optimized for high performance, low power, and ease  
of use. The product operates up to a 200 MSPS conversion rate  
and is optimized for outstanding dynamic performance in  
wideband carrier and broadband systems. All necessary  
functions, including track-and-hold (T/H) and reference, are  
included on the chip to provide a complete conversion solution.  
1. High performance.  
Maintains 60 dB SNR @ 200 MSPS with a 70 MHz input.  
2. Low power.  
Consumes only 1.25 W @ 200 MSPS.  
3. Ease of use.  
LVDS output data and output clock signal allow interface  
to current FPGA technology. The on-chip reference and  
sample-and-hold function provide flexibility in system  
design. Use of a single 3.3 V supply simplifies system  
power supply design.  
The ADC requires a 3.3 V power supply and a differential  
sample clock for full performance operation. The digital outputs  
are LVDS compatible and support both twos complement and  
offset binary format. A data clock output is available to ease  
data capture.  
4. Out-of-range (OR).  
The OR output bit indicates when the input signal is  
beyond the selected input range.  
Fabricated on an advanced BiCMOS process, the AD9411 is  
available in a 100-lead surface-mount plastic package (e-PAD  
TQFP-100) specified over the industrial temperature range  
(–40°C to +85°C).  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  

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