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AD9430_10

更新时间: 2024-10-28 12:27:19
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
44页 1513K
描述
12-Bit, 170/210 MSPS 3.3 V A/D Converter

AD9430_10 数据手册

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12-Bit, 170/210 MSPS  
3.3 V A/D Converter  
AD9430  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
SNR = 65 dB @ fIN = 70 MHz @ 210 MSPS  
ENOB of 10.6 @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS)  
SFDR = 80 dBc @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS)  
Excellent linearity:  
DRGND DRVDD  
AGND  
AVDD  
SENSE  
VREF  
AD9430  
SCALABLE  
REFERENCE  
DNL = 0.3 LSB (typical)  
INL = 0.5 LSB (typical)  
2 output data options:  
Demultiplexed 3.3 V CMOS outputs each @ 105 MSPS  
Interleaved or parallel data output option  
LVDS at 210 MSPS  
700 MHz full-power analog bandwidth  
On-chip reference and track-and-hold  
Power dissipation = 1.3 W typical @ 210 MSPS  
1.5 V input voltage range  
LVDS  
OUTPUTS  
ADC  
VIN+  
VIN–  
DATA,  
12  
TRACK-  
AND-HOLD  
12-BIT  
PIPELINE  
CORE  
OVERRANGE  
IN LVDS OR  
2-PORT CMOS  
CMOS  
OUTPUTS  
DS+  
DS–  
SELECT CMOS  
OR LVDS  
DCO+  
DCO–  
CLOCK  
MANAGEMENT  
CLK+  
CLK–  
3.3 V supply operation  
S1  
S2  
S4  
S5  
Output data format option  
Figure 1.  
Data sync input and data clock output provided  
Clock duty cycle stabilizer  
APPLICATIONS  
GENERAL DESCRIPTION  
Wireless and wired broadband communications  
Cable reverse path  
Communications test equipment  
Radar and satellite subsystems  
Power amplifier linearization  
The AD9430 is a 12-bit, monolithic, sampling analog-to-digital  
converter (ADC) optimized for high performance, low power,  
and ease of use. The product operates up to a 210 MSPS  
conversion rate and is optimized for outstanding dynamic  
performance in wideband carrier and broadband systems. All  
necessary functions, including a track-and-hold (T/H) and  
reference, are included on the chip to provide a complete  
conversion solution.  
PRODUCT HIGHLIGHTS  
1. High performance.  
Maintains 65 dB SNR @ 210 MSPS with a 65 MHz input.  
2. Low power.  
Consumes only 1.3 W @ 210 MSPS.  
3. Ease of use.  
The ADC requires a 3.3 V power supply and a differential  
ENCODE clock for full performance operation. The digital  
outputs are TTL/CMOS or LVDS compatible and support either  
twos complement or offset binary format. Separate output  
power supply pins support interfacing with 3.3 V CMOS logic.  
LVDS output data and output clock signal allow interface  
to current FPGA technology. The on-chip reference and  
sample-and-hold provide flexibility in system design. Use  
of a single 3.3 V supply simplifies system power supply  
design.  
Two output buses support demultiplexed data up to 105 MSPS  
rates in CMOS mode. A data sync input is supported for proper  
output data port alignment in CMOS mode, and a data clock  
output is available for proper output data timing. In LVDS  
mode, the chip provides data at the ENCODE clock rate.  
4. Out of range (OR) feature.  
The OR output bit indicates when the input signal is  
beyond the selected input range.  
5. Pin compatible with 10-bit AD9411 (LVDS only).  
Fabricated on an advanced BiCMOS process, the AD9430 is  
available in a 100-lead, surface-mount plastic package  
(100 e-PAD TQFP) specified over the industrial temperature  
range (–40°C to +85°C).  
.
Rev. E  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
www.analog.com  
Fax: 781.461.3113 ©2005–2010 Analog Devices, Inc. All rights reserved.  

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