Datasheet > AD9371BBCZ-REEL

AD9371BBCZ-REEL

更新时间： 2022-02-26 12:08:17

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
60页	1888K
描述
Dual differential transmitters

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AD9371BBCZ-REEL 数据手册

Data Sheet

AD9371

Table 8. Example Rx/Tx Interface Rates (Two Rx/Two Tx Channels, Maximum JESD Lane Rates)

Tx/Tx Synthesis/

Rx Bandwidth (MHz)

Tx Input

Rate (MSPS)

Rx Output

Rate (MSPS)

JESD204B Lane Rate

(Mbps), Two Tx/Two Rx of Lanes) Tx/Rx Reference Clock Options (MHz)

JESD204B (No.

100/250/100

75/200/100

20/100/40

20/100/20

307.2

153.6

122.88

61.44

30.72

6144

4/2

4/1

122.88, 153.6, 245.76, 307.2

122.88, 245.76

245.76

122.88

4915.2

2457.6

122.88, 245.76

TRANSMITTER

HALF-BAND

FILTER 2

QUADRATURE

ERROR

CORRECTION

TRANSMITTER

HALF-BAND

FILTER 1

DIGITAL

TRANSMITTER FIR

(INTERPOLATION

1, 2, 4)

I/Q DAC

JESD204B

GAIN

Figure 240. Example Tx Data Path Filter Implementation

DEC5

RECEIVER

HALF-BAND

FILTER 3

RECEIVER

HALF-BAND

FILTER 2

RECEIVER

HALF-BAND

FILTER 1

RFIR

(DECIMATION

1, 2, 4)

QEC

CORRECTION

FILTER

DIGITAL

GAIN

JESD204B

ADC

CORRECTION

Figure 241. Data Rx Data Path Filter Implementation

POWER SUPPLY SEQUENCE

Table 9. Dual-Function Boundary Scan Test Pins

The AD9371 requires a specific power-up sequence to avoid

undesired power-up currents. The optimal power-on sequence

starts the process by powering up the VDIG and the VDDA_1P3

(analog) supplies simultaneously. If they cannot power up

simultaneously, the VDIG supply must power up first. The

VDDA_3P3, VDDA_1P8, and JESD_VTT_DES supplies

must then power up after the VDIG and VDDA_1P3 supplies.

Note that the VDD_IF supply can power up at any time. It is

Mnemonic JTAG Mnemonic Description

GPIO_4

GPIO_5

GPIO_6

GPIO_7

GPIO_18

TRST

TDO

TDI

TMS

TCK

Test access port reset

Test data output

Test data input

Test access port mode select

Test clock

Table 10. JTAG Modes

Test Pin Level

GPIO_0 to GPIO_3

Description

RESET

also recommended to toggle the

signal after power has

XXXX¹

Normal operation

JTAG mode with LVDS

JESD204B sync signals

stabilized prior to configuration. Follow the reverse order of

the power-up sequence to power-down.

1001

Note that VDDA_1P3 refers to all analog 1.3 V supplies

including the following: VDDA_BB, VDDA_CLKSYNTH,

VDDA_TXLO, VDDA_RXRF, VDDA_RXSYNTH,

VDDA_RXVCO, VDDA_RXTX, VDDA_TXSYNTH,

VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH,

VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO.

1011

JTAG mode with CMOS

JESD204B sync signals

¹X means don’t care.

JTAG BOUNDARY SCAN

The AD9371 provides support for a JTAG boundary scan.

There are five dual-function pins associated with the JTAG

interface. These pins, listed in Table 9, are used to access the

on-chip test access port. To enable the JTAG functionality,

set the GPIO_0 through GPIO_3 pins according to Table 10

depending on how the desired JESD204B sync pin (that is,

SYNCINB0+, SYNCINB0−, SYNCINB1+, SYNCINB1−,

SYNCBOUTB0+, or SYNCBOUTB0−) is configured in the

software (LVDS or CMOS mode). Pull the TEST pin high to

enable the JTAG mode.

Rev. A | Page 59 of 60

1...56 57 585960

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AD9371BBCZ-REEL 替代型号

型号	品牌	替代类型	描述	数据表
AD9371BBCZ	ADI	完全替代	Dual differential transmitters

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