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AD9267EBZ

更新时间: 2024-10-28 06:36:15
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亚德诺 - ADI /
页数 文件大小 规格书
24页 524K
描述
10 MHz Bandwidth, 640 MSPS Dual Continuous Time Sigma-Delta Modulator

AD9267EBZ 数据手册

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10 MHz Bandwidth, 640 MSPS  
Dual Continuous Time Sigma-Delta Modulator  
AD9267  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
AVDD PDWNB  
PDWNA  
DRVDD  
SNR: 83 dB (85 dBFS) to 10 MHz input  
SFDR: −88 dBc to 10 MHz input  
Noise figure: 15 dB  
Input impedance: 1 kΩ  
Power: 416 mW  
10 MHz real or 20 MHz complex bandwidth  
1.8 V analog supply operation  
On-chip PLL clock multiplier  
On-chip voltage reference  
Twos complement data format  
640 MSPS, 4-bit LVDS data output  
Serial control interface (SPI)  
OR±A  
D3±A  
VIN+A  
VIN–A  
Σ-Δ  
MODULATOR  
D0±A  
PLL_LOCKED  
PLLMULT4  
PLLMULT3  
PLLMULT2  
AD9267  
CLK+  
CLK–  
PHASE-  
LOCKED  
LOOP  
VREF  
CFILT  
DCO±  
D3±B  
VIN–B  
VIN+B  
Σ-Δ  
MODULATOR  
D0±B  
OR±B  
APPLICATIONS  
SERIAL  
INTERFACE  
Baseband quadrature receivers: CDMA2000, W-CDMA,  
multicarrier GSM/EDGE, 802.16x, and LTE  
Quadrature sampling instrumentation  
AGND  
SDIO/  
SCLK/  
CSB DGND  
PLLMULT1 PLLMULT0  
GENERAL DESCRIPTION  
Figure 1.  
The AD9267 is a dual continuous time (CT) sigma-delta (Σ-Δ)  
modulator with −88 dBc of dynamic range over 10 MHz real  
or 20 MHz complex bandwidth. The combination of high  
dynamic range, wide bandwidth, and characteristics unique  
to the continuous time Σ-Δ modulator architecture makes the  
AD9267 an ideal solution for wireless communication systems.  
The AD9267 operates on a 1.8 V power supply, consuming  
416 mW. The AD9267 is available in a 64-lead LFCSP and  
is specified over the industrial temperature range (−40°C  
to +85°C).  
PRODUCT HIGHLIGHTS  
1. Continuous time Σ-Δ architecture efficiently achieves high  
dynamic range and wide bandwidth.  
2. Passive input structure reduces or eliminates the require-  
ments for a driver amplifier.  
3. An oversampling ratio of 32× and high order loop filter  
provide excellent alias rejection, reducing or eliminating  
the need for antialiasing filters.  
4. Operates from a single 1.8 V power supply.  
5. A standard serial port interface (SPI) supports various  
product features and functions.  
The AD9267 has a resistive input impedance that significantly  
relaxes the requirements of the driver amplifier. In addition, a  
32× oversampled fifth-order continuous time loop filter attenuates  
out-of-band signals and aliases, reducing the need for external  
filters at the input. The low noise figure of 15 dB relaxes the  
linearity requirements of the front-end signal chain components,  
and the high dynamic range reduces the need for an automatic  
gain control (AGC) loop.  
A differential input clock controls all internal conversion cycles.  
An external clock input or the integrated integer-N PLL provides  
the 640 MHz internal clock needed for the oversampled conti-  
nuous time Σ-Δ modulator. The digital output data is presented  
as 4-bit, LVDS at 640 MSPS in twos complement format. A data  
clock output (DCO) is provided to ensure proper latch timing  
with receiving logic. Additional digital signal processing may be  
required on the 4-bit modulator output to remove the out-of-band  
noise and to reduce the sample rate.  
6. Features a low pin count, high speed LVDS interface with  
data output clock.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2009 Analog Devices, Inc. All rights reserved.  
 
 
 
 
 

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