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AD9268-105EBZ PDF预览

AD9268-105EBZ

更新时间: 2024-10-29 01:03:47
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
45页 2071K
描述
1.8 V Dual Analog-to-Digital Converter (ADC)

AD9268-105EBZ 数据手册

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16-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual  
Analog-to-Digital Converter (ADC)  
AD9268  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
SDIO/ SCLK/  
SNR = 78.2 dBFS @ 70 MHz and 125 MSPS  
SFDR = 88 dBc @ 70 MHz and 125 MSPS  
Low power: 750 mW @ 125 MSPS  
AVDD  
CSB  
DRVDD  
DCS  
DFS  
SPI  
AD9268  
1.8 V analog supply operation  
ORA  
1.8 V CMOS or LVDS output supply  
Integer 1-to-8 input clock divider  
IF sampling frequencies to 300 MHz  
−153.6 dBm/Hz small-signal input noise with 200 Ω input  
impedance @ 70 MHz and 125 MSPS  
Optional on-chip dither  
Programmable internal ADC voltage reference  
Integrated ADC sample-and-hold inputs  
Flexible analog input range: 1 V p-p to 2 V p-p  
Differential analog inputs with 650 MHz bandwidth  
ADC clock duty cycle stabilizer  
PROGRAMMING DATA  
CMOS/LVDS  
D15A (MSB)  
TO  
D0A (LSB)  
VIN+A  
VIN–A  
16  
ADC  
OUTPUT BUFFER  
CLK+  
CLK–  
DIVIDE 1  
TO 8  
VREF  
SENSE  
DCOA  
DCOB  
DUTY CYCLE  
STABILIZER  
DCO  
GENERATION  
REF  
SELECT  
VCM  
RBIAS  
VIN–B  
VIN+B  
ORB  
D15B (MSB)  
TO  
D0B (LSB)  
16  
CMOS/LVDS  
OUTPUT BUFFER  
ADC  
95 dB channel isolation/crosstalk  
Serial port control  
MULTICHIP  
SYNC  
User-configurable, built-in self-test (BIST) capability  
Energy-saving power-down modes  
AGND  
SYNC  
PDWN  
OEB  
NOTES  
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;  
SEE FIGURE 7 FORLVDS PIN NAMES.  
APPLICATIONS  
Figure 1.  
Communications  
Diversity radio systems  
PRODUCT HIGHLIGHTS  
Multimode digital receivers (3G)  
GSM, EDGE, W-CDMA, LTE,  
CDMA2000, WiMAX, TD-SCDMA  
I/Q demodulation systems  
Smart antenna systems  
General-purpose software radios  
Broadband data applications  
Ultrasound equipment  
1. On-chip dither option for improved SFDR performance  
with low power analog input.  
2. Proprietary differential input that maintains excellent SNR  
performance for input frequencies up to 300 MHz.  
3. Operation from a single 1.8 V supply and a separate digital  
output driver supply accommodating 1.8 V CMOS or  
LVDS outputs.  
4. Standard serial port interface (SPI) that supports various  
product features and functions, such as data formatting  
(offset binary, twos complement, or gray coding), enabling  
the clock DCS, power-down, test modes, and voltage  
reference mode.  
5. Pin compatibility with the AD9258, allowing a simple  
migration from 16 bits to 14 bits. The AD9268 is also pin  
compatible with the AD9251, AD9231, and AD9204 family  
of products for lower sample rate, low power applications.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2009 Analog Devices, Inc. All rights reserved.  
 
 

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