Quad, 12-bit, 40/65 MSPS
Serial LVDS 1.8 V A/D Converter
AD9228
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AVDD
PDWN
Four ADCs integrated into 1 package
119 mW ADC power per channel at 65 MSPS
SNR = 70 dB (to Nyquist)
DRVDD
DRGND
AD9228
12
VIN+A
VIN–A
SERIAL
LVDS
D+A
D–A
PIPELINE
ADC
Excellent linearity
DNL = 0.3 LSB (typical)
INL = 0.4 LSB (typical)
12
12
VIN+B
VIN–B
PIPELINE
ADC
SERIAL
LVDS
D+B
D–B
Serial LVDS (ANSI-644, default)
Low power reduced signal option, IEEE 1596.3 similar
Data and frame clock outputs
315 MHz full power analog bandwidth
2 V p-p input voltage range
VIN+C
VIN–C
SERIAL
LVDS
D+C
D–C
PIPELINE
ADC
12
VIN+D
VIN–D
SERIAL
LVDS
D+D
D–D
PIPELINE
ADC
VREF
1.8 V supply operation
Serial port control
FCO+
FCO–
SENSE
+
0.5V
–
DATA RATE
REFT
REFB
REF
SELECT
MULTIPLIER
Full-chip and individual-channel power-down modes
Flexible bit orientation
SERIAL PORT
INTERFACE
DCO+
DCO–
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
SCLK/DTP
RBIASAGND CSB SDIO/ODM
CLK+ CLK–
Figure 1.
capturing data on the output and a frame clock (FCO) for
APPLICATIONS
signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI®).
Test equipment
GENERAL DESCRIPTION
The AD9228 is available in a Pb-free, 48-lead LFCSP package. It is
specified over the industrial temperature range of −40°C to +85°C.
The AD9228 is a quad, 12-bit, 40/65 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit that
is designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 65 MSPS and
is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
PRODUCT HIGHLIGHTS
1. Small Footprint. Four ADCs are contained in a small, space-
saving package; low power of 119 mW/channel at 65 MSPS.
2. Ease of Use. A data clock output (DCO) is provided that
operates up to 390 MHz and supports double data rate
operation (DDR).
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
3. User Flexibility. Serial port interface (SPI) control offers a wide
range of flexible features to meet specific system requirements.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock (DCO) for
4. Pin-Compatible Family. This includes the AD9287 (8-bit),
AD9219 (10-bit), and AD9259 (14-bit).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
5秒后页面跳转
三星深化印度制造布局，供应链本地化进程加速
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
纳微科技震撼发布GaNSlim革新氮化镓功率芯片
意法半导体发布第四代SiC技术，助力电动汽车电驱
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
