Quad, 12-Bit, 40/65 MSPS
Serial LVDS 1.8 V A/D Converter
AD9228
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AVDD
PDWN
DRVDD
DRGND
4 ADCs integrated into 1 package
119 mW ADC power per channel at 65 MSPS
SNR = 70 dB (to Nyquist)
AD9228
12
VIN + A
VIN – A
SERIAL
LVDS
D + A
D – A
PIPELINE
ADC
ENOB = 11.3 bits
SFDR = 82 dBc (to Nyquist)
Excellent linearity
DNL = 0.3 LSB (typical)
12
12
VIN + B
VIN – B
PIPELINE
ADC
SERIAL
LVDS
D + B
D – B
VIN + C
VIN – C
SERIAL
LVDS
D + C
D – C
INL = 0.4 LSB (typical)
PIPELINE
ADC
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
315 MHz full-power analog bandwidth
2 V p-p input voltage range
12
VIN + D
VIN – D
SERIAL
LVDS
D + D
D – D
PIPELINE
ADC
VREF
FCO+
FCO–
SENSE
+
0.5V
–
DATA RATE
MULTIPLIER
1.8 V supply operation
Serial port control
REFT
REFB
REF
SELECT
SERIAL PORT
INTERFACE
DCO+
DCO–
Full-chip and individual-channel power-down modes
Flexible bit orientation
SCLK/DTP
RBIASAGND CSB SDIO/ODM
CLK+ CLK–
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
Figure 1.
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-
channel power-down is supported and typically consumes less
than 2 mW when all channels are disabled.
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI).
Test equipment
GENERAL DESCRIPTION
The AD9228 is available in an RoHS compliant, 48-lead LFCSP. It is
specified over the industrial temperature range of −40°C to +85°C.
The AD9228 is a quad, 12-bit, 40/65 MSPS analog-to-digital con-
verter (ADC) with an on-chip sample-and-hold circuit designed
for low cost, low power, small size, and ease of use. The product
operates at a conversion rate of up to 65 MSPS and is optimized for
outstanding dynamic performance and low power in applications
where a small package size is critical.
PRODUCT HIGHLIGHTS
1. Small Footprint. Four ADCs are contained in a small, space-
saving package.
2. Low power of 119 mW/channel at 65 MSPS.
3. Ease of Use. A data clock output (DCO) is provided that
operates at frequencies of up to 390 MHz and supports
double data rate (DDR) operation.
4. User Flexibility. The SPI control offers a wide range of flexible
features to meet specific system requirements.
5. Pin-Compatible Family. This includes the AD9287 (8-bit),
AD9219 (10-bit), and AD9259 (14-bit).
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2007 Analog Devices, Inc. All rights reserved.
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