Preliminary Data Sheet
AD9084
Apollo MxFE Quad, 16-Bit, 28 GSPS RF DAC and Quad, 12-Bit, 20 GSPS RF ADC
► Fast detect with low latency for fast AGC control
► Signal monitor for slow AGC control
► Auxiliary features
► Power amplifier downstream protection circuitry
► On-chip temperature monitoring unit
► TDD power savings option
► Total power consumption range dependent on device configura-
tion : 20 W to 30 W
► 24 mm × 26 mm, 899-ball BGA with 0.8 mm pitch
► Operating junction temperature (TJ): −40°C to +110°C
FEATURES
► Flexible reconfigurable common platform design
► 4 DACs and 4 ADCs (4D4A)
► Usable RF Analog bandwidth up to 18 GHz
► Maximum DAC/ADC sample rate up to 28 GSPS/20 GSPS
► DAC to ADC sample rate ratios of 1 and 2
► Clocking
► On-chip PLL (7 GHz to 14 GHz)
► External RFCLK input up to 20 GHz
► Multichip synchronization via subclass1
► Single-ended (SE) or differential (DIFF) ADC inputs
► Two separate versions, both 50 Ω input impedance
► Single-ended version with on-chip wide bandwidth balun
► Differential ADC AC performance at 20 GSPS
► Full-scale input voltage: 500 mV p-p/−2 dBm
► Noise density: −150 dBFS/Hz at −20 dBFS at 2 GHz
► HD2/HD3: −65 dBFS/−70 dBFS at −7 dBFS at 2 GHz
APPLICATIONS
► Radar and communications
► L/S/C/X/Ku band radar and electronic warfare
► Phase array system
► Broadband communications systems
► Electronic test and measurement systems
► Satellite communications
► IMD3: −75 dBFS at – 13 dBFS/tone at 2 GHz
► DAC AC performance at 28 GSPS
► Full-scale output power: −2.1 dBm at 2 GHz
► IMD3: −75 dBc at – 13 dBFS/tone at 2 GHz to 10 GHz
► NSD (shuffling disabled): −164 dBFS/Hz at 0 dBFS at 2 GHz
► Versatile digital features
► Microwave point-to-point, X-band and 5G mmWave
FUNCTIONAL BLOCK DIAGRAM
► Supports real or complex digital data (8-, 12-, 16-bit)
► Configurable DDC and DUC
► 8 fine complex DUCs and 4 coarse complex DUCs
► 8 fine complex DDCs and 4 coarse complex DDCs
► Option to bypass fine and coarse DUC/DDC
► DUC/DDC alias rejection
► 85 dB for interpolation filters
► 100 dB for decimation filters
► Fractional sample rate converter (FSRC)
► Programmable FIR filters for transmit/receive
► Multiple loopback (ADC to DAC) supported
► ~45 ns without DSP path
► Dynamic configuration through SPI/HSCI/GPIO
► Spectrum sniffer/monitor
► Interfaces
► SPI
► High-Speed Control Interface (HSCI)
► JESD204B/JESD204C: 20 Gbps/32.5 Gbps
► 24 lanes for Rx, 24 lanes for Tx
Figure 1. Functional Block Diagram
► Receive AGC support
Rev. PrA
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