Low Power, 14-Bit, 180 MSPS, Digital-to-Analog
Converter and Waveform Generator
Data Sheet
AD9102
The DDS is a 14-bit output, up to 180 MSPS master clock sine
wave generator with a 24-bit tuning word, allowing 10.8 Hz/LSB
frequency resolution.
FEATURES
On-chip 4096 × 14-bit pattern memory
On-chip DDS
Power dissipation @ 3.3 V, 4 mA output
96.54 mW @ 180 MSPS
Sleep mode: <5 mW @ 3.3 V
Supply voltage: 1.8 V to 3.3 V
SFDR to Nyquist
87 dBc @ 10 MHz output
Phase noise @ 1 kHz offset, 180 MSPS, 8 mA: −150 dBc/Hz
Differential current outputs: 8 mA max @ 3.3 V
SRAM data can include directly generated stored waveforms,
amplitude modulation patterns applied to DDS outputs, or DDS
frequency tuning words.
An internal pattern control state machine lets the user program
the pattern period for the DAC as well the start delay within the
pattern period for the signal output on the DAC .
A SPI interface is used to configure the digital waveform
generator and load patterns into the SRAM.
Small footprint, 32-lead, 5 mm × 5 mm LFCSP with 3.6 mm ×
3.6 mm exposed paddle, and Pb-free package
A gain adjustment factor and an offset adjustment are applied to
the digital signal on their way into the DAC.
APPLICATIONS
The AD9102 offers exceptional ac and dc performance and
supports DAC sampling rates of up to 180 MSPS.
Medical instrumentation
Portable instrumentation
The flexible power supply operating range of 1.8 V to 3.3 V and
low power dissipation of the AD9102 make it well suited for
portable and low power applications.
Signal generators, arbitrary waveform generators
Automotive radar
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9102 TxDAC® and waveform generator is a high perfor-
mance digital-to-analog converter (DAC) integrating on-chip
pattern memory for complex waveform generation with a direct
digital synthesizer (DDS).
1. High Integration.
On-chip DDS and 4096 × 14 pattern memory.
2. Low Power.
Power-down mode provides for low power idle periods.
FUNCTIONAL BLOCK DIAGRAM
1V
AD9102
SPI
INTERFACE
10kΩ
AGND
BAND
GAP
STOP ADDR
START ADDR
START DELAY
R
SET1
16kΩ
DAC
TIMERS + STATE MACHINE
ADDRESS
TRIGGER
I
REF
100µA
IOUTP
IOUTN
AVDD1
AVDD2
DAC
GAIN
OFFSET
SRAM
PHASE
TUNING WORD
DAC CLOCK
DDS
DDS
1.8V
LDO
CLOCK
DIST
1.8V
LDOs
Figure 1.
Rev. 0
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