16-Channel, 8-Bit
Multiplying DAC
a
AD8600*
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
16 Independently Addressable Voltage Outputs
Full-Scale Set by External Reference
2 µs Settling Tim e
Double Buffered 8-Bit Parallel Input
High Speed Data Load Rate
Data Readback
V
V
V
V
CC
RS
LD
R/W
DD1
DD2
REF
O0
O1
O2
O3
O4
O5
O6
O7
CS
EN
CONTROL
LOGIC
A3
A2
A1
A0
ADDRESS
DECODE
16 x 8
DAC
REGISTERS
16
Operates from Single +5 V
Optional ±6 V Supply Extends Output Range
8-BIT
DACS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
O8
O9
16 x 8
INPUT
O10
O11
O12
O13
O14
O15
APPLICATIONS
Phased Array Ultrasound & Sonar
Pow er Level Setting
Receiver Gain Setting
Autom atic Test Equipm ent
LCD Clock Level Setting
REGISTERS
AD8600
D
V
EE
D
DACGND
GND2
GND1
At system power up or during fault recovery the reset (RS) pin
forces all DAC registers into the zero state which places zero
volts at all DAC outputs.
GENERAL D ESCRIP TIO N
T he AD8600 contains 16 independent voltage output digital-to-
analog converters that share a common external reference input
voltage. Each DAC has its own DAC register and input register
to allow double buffering. An 8-bit parallel data input, four ad-
dress pins, a CS select, a LD, EN, R/W, and RS provide the
digital interface.
T he AD8600 is offered in the PLCC-44 package. T he device is
designed and tested for operation over the extended industrial
temperature range of –40°C to +85°C.
V
LD•EN
R/W•CS•ADDR•EN
V
REF
V
DD2
DD1
T he AD8600 is constructed in a monolithic CBCMOS process
which optimizes use of CMOS for logic and bipolar for speed
and precision. T he digital-to-analog converter design uses volt-
age mode operation ideally suited to single supply operation.
V
CC
INPUT
REGISTER
R-2R
DAC
DAC
REGISTER
DB7...DB0
O
X
T he internal DAC voltage range is fixed at DACGND to VREF
T he voltage buffers provide an output voltage range that ap-
proaches ground and extends to 1.0 V below VCC. Changes in
reference voltage values and digital inputs will settle within
±1 LSB in 2 µs.
.
RS
RS
D
GND2
DACGND
V
EE
D
GND1
R/W•CS•ADDRESS
Data is preloaded into the input registers one at a time after the
internal address decoder selects the input register. In the write
mode (R/W low) data is latched into the input register during
the positive edge of the EN pulse. Pulses as short as 40 ns can
be used to load the data. After changes have been submitted to
the input registers, the DAC registers are simultaneously up-
dated by a common load EN × LD strobe. T he new analog out-
put voltages simultaneously appear on all 16 outputs.
Figure 1. Equivalent DAC Channel
*P atent pending.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood. MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703