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AD8317-EVALZ PDF预览

AD8317-EVALZ

更新时间: 2024-01-15 04:14:46
品牌 Logo 应用领域
亚德诺 - ADI 控制器
页数 文件大小 规格书
20页 782K
描述
1 MHz to 10 GHz, 55 dB Log Detector/Controller

AD8317-EVALZ 技术参数

Source Url Status Check Date:2013-05-01 14:56:25.48是否无铅: 含铅
是否Rohs认证: 符合生命周期:Active
零件包装代码:DIE包装说明:DIE,
针数:0Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.73Is Samacsys:N
模拟集成电路 - 其他类型:LOG OR ANTILOG AMPLIFIER标称带宽:10000 MHz
JESD-30 代码:R-XUUC-N8湿度敏感等级:1
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:DIE
封装形状:RECTANGULAR封装形式:UNCASED CHIP
峰值回流温度(摄氏度):260认证状态:Not Qualified
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:BIPOLAR温度等级:INDUSTRIAL
端子形式:NO LEAD端子位置:UPPER
处于峰值回流温度下的最长时间:30Base Number Matches:1

AD8317-EVALZ 数据手册

 浏览型号AD8317-EVALZ的Datasheet PDF文件第13页浏览型号AD8317-EVALZ的Datasheet PDF文件第14页浏览型号AD8317-EVALZ的Datasheet PDF文件第15页浏览型号AD8317-EVALZ的Datasheet PDF文件第17页浏览型号AD8317-EVALZ的Datasheet PDF文件第18页浏览型号AD8317-EVALZ的Datasheet PDF文件第19页 
AD8317  
EVALUATION BOARD  
Table 5. Evaluation Board (Rev. A) Configuration Options  
Component  
VPOS, GND  
R1, C1, C2  
Function  
Default Conditions  
Supply and Ground Connections.  
Not applicable  
Input Interface.  
R1 = 52.3 Ω (Size 0402)  
C1 = 47 nF (Size 0402)  
C2 = 47 nF (Size 0402)  
The 52.3 Ω resistor in Position R1 combines with the internal input impedance  
of the AD8317 to give a broadband input impedance of about 50 Ω. C1 and C2  
are dc-blocking capacitors. A reactive impedance match can be implemented  
by replacing R1 with an inductor and C1 and C2 with appropriately valued  
capacitors.  
R5, R7  
Temperature Compensation Interface.  
R5 = 200 Ω (Size 0402)  
R7 = open (Size 0402)  
The internal temperature compensation network is optimized for input signals  
up to 3.6 GHz when R7 is 10 kΩ. This circuit can be adjusted to optimize  
performance for other input frequencies by changing the value of the resistor  
in Position R7. See Table 4 for specific RTADJ resistor values.  
R2, R3, R4, R6, RL, CL  
Output Interface—Measurement Mode.  
R2 = 0 Ω (Size 0402)  
In measurement mode, a portion of the output voltage is fed back to the VSET  
pin via R2. The magnitude of the slope of the VOUT output voltage response  
can be increased by reducing the portion of VOUT that is fed back to VSET. R6  
can be used as a back-terminating resistor or as part of a single-pole, low-pass  
filter.  
R3 = open (Size 0402)  
R4 = open (Size 0402)  
R6 = 1 kΩ (Size 0402)  
RL = CL = open (Size 0402)  
R2, R3  
Output Interface—Controller Mode.  
R2 = open (Size 0402)  
In this mode, R2 must be open. In controller mode, the AD8317 can control the R3 = open (Size 0402)  
gain of an external component. A setpoint voltage is applied to Pin VSET, the  
value of which corresponds to the desired RF input signal level applied to the  
AD8317 RF input. A sample of the RF output signal from this variable gain  
component is selected, typically via a directional coupler, and applied to the  
AD8317 RF input. The voltage at the VOUT pin is applied to the gain control of  
the variable gain element. A control voltage is applied to the VSET pin. The  
magnitude of the control voltage can optionally be attenuated via the voltage  
divider comprising R2 and R3, or a capacitor can be installed in Position R3 to  
form a low-pass filter along with R2.  
C4, C5  
C3  
Power Supply Decoupling.  
C4 = 0.1 ꢀF (Size 0603)  
C5 = 100 pF (Size 0402)  
The nominal supply decoupling consists of a 100 pF filter capacitor placed  
physically close to the AD8317 and a 0.1 ꢀF capacitor placed nearer to the  
power supply input pin.  
Filter Capacitor.  
C3 = 8.2 pF (Size 0402)  
The low-pass corner frequency of the circuit that drives the VOUT pin can be  
lowered by placing a capacitor between CLPF and ground. Increasing this  
capacitor increases the overall rise/fall time of the AD8317 for pulsed input  
signals. See the Output Filtering section for more details.  
VPOS  
C4  
TADJ  
GND  
R5  
200  
0.1µF  
C5  
VOUT_ALT  
R4  
R7  
OPEN  
OPEN  
100pF  
C1  
R6  
V
OUT  
1kΩ  
47nF  
CL  
RL  
8
7
6
5
OPEN OPEN  
INLO VPOS  
TADJ  
VOUT  
R2  
R1  
52.3Ω  
AD8317  
0Ω  
INHI  
1
COMM CLPF  
VSET  
4
2
3
RFIN  
C2  
C3  
8.2pF  
V
SET  
47nF  
R3  
OPEN  
Figure 36. Evaluation Board Schematic  
Rev. B | Page 16 of 20  
 

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