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AD8142-EVALZ PDF预览

AD8142-EVALZ

更新时间： 2024-02-01 22:53:29
品牌 Logo 应用领域
亚德诺 - ADI 驱动器
页数 文件大小 规格书
24页 451K
描述
Low Cost, Triple Differential Drivers

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中文翻译

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AD8142-EVALZ 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN,针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.7
差分输出：YES驱动器位数：3
输入特性：DIFFERENTIAL接口集成电路类型：LINE DRIVER
接口标准：GENERAL PURPOSEJESD-30 代码：S-XQCC-N24
JESD-609代码：e3长度：4 mm
湿度敏感等级：1功能数量：3
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
认证状态：Not Qualified最大接收延迟：
座面最大高度：0.8 mm最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：4 mmBase Number Matches：1

AD8142-EVALZ 数据手册

 浏览型号AD8142-EVALZ的Datasheet PDF文件第18页浏览型号AD8142-EVALZ的Datasheet PDF文件第19页浏览型号AD8142-EVALZ的Datasheet PDF文件第20页浏览型号AD8142-EVALZ的Datasheet PDF文件第21页浏览型号AD8142-EVALZ的Datasheet PDF文件第23页浏览型号AD8142-EVALZ的Datasheet PDF文件第24页 
AD8141/AD8142  
2.25  
2.00  
1.75  
1.50  
1.25  
1.00  
0.75  
0.50  
0.25  
0
17.5  
12.5  
SYNC LEVEL = 0.5V  
2kΩ  
G
CM  
AD8142  
1kΩ  
1kΩ  
+IN R  
–OUT R  
+OUT R  
+
V
R
OCM  
R
B
CM  
CM  
–
–IN R  
V
2kΩ  
SYNC  
7.5  
H
SYNC  
H
V
SYNC  
SYNC  
2kΩ  
2.5  
SYNC LEVEL  
+IN G  
1kΩ  
1kΩ  
–OUT G  
+OUT G  
+
V
G
OCM  
×2  
–2.5  
–
–IN G  
0
40  
80  
120 160 200 240 280 320 360 400  
2kΩ  
2kΩ  
TIME (ns)  
Figure 48. AD8142 Sync-On-Common-Mode Signals in Single 5 V Application  
1kΩ  
1kΩ  
LAYOUT AND POWER SUPPLY DECOUPLING  
CONSIDERATIONS  
–OUT B  
+OUT B  
+IN B  
–IN B  
+
V
B
OCM  
–
When designing with the AD8141 and AD8142, adhere to  
standard high speed printed circuit board (PCB) layout practices.  
A solid ground plane is recommended and good wideband power  
supply decoupling networks should be placed as close as possible  
to the supply pins. Small surface-mount ceramic capacitors are  
recommended for these networks, and tantalum capacitors are  
recommended for bulk supply decoupling.  
2kΩ  
DIS  
V
WEIGHTING EQUATIONS ON +5V SUPPLY:  
OCM  
K
2
RED V  
=
(V  
– H  
) + 1.5V  
OCM  
SYNC  
SYNC  
K
2
GREEN V  
=
(–2V  
) + 1.5V  
OCM  
SYNC  
K
2
BLUE V  
=
(V  
+ H  
) + 1.5V  
OCM  
SYNC  
SYNC  
AMPLIFIER-TO-AMPLIFIER ISOLATION  
Figure 47. AD8142 Conceptual Sync-On-Common-Mode Encoding Scheme  
The least amount of isolation between the three AD8142 amplifiers  
exists between the green and red channels (Amplifier A and  
Amplifier B for the AD8141). This is, therefore, viewed as the  
worst-case isolation, which is reflected in Table 1 and the  
Theory of Operation section.  
The transmitted common-mode sync signal magnitudes are  
scaled by applying a dc voltage to the SYNC LEVEL input,  
referenced to the negative supply. The difference between the  
voltage applied to the SYNC LEVEL input and the negative supply  
sets the peak deviation of the encoded sync signals about the  
midsupply common-mode voltage. For example, with the SYNC  
LEVEL input set at VS− + 500 mV, the deviation of the encoded  
sync pulses about the nominal midsupply common-mode voltage  
is nominally 500 mV. The equations in Figure 47 describe how  
the VSYNC and HSYNC signals are encoded on each color’s midsupply  
common-mode signal. In these equations, the weights of the VSYNC  
and HSYNC signals are 1 (that is, +1 for high, −1 for low), and the  
constant, K, is equal to the peak deviation of the encoded sync  
signals.  
EXPOSED PADDLE (EPAD)  
The 24-lead LFCSP package has an exposed paddle on the  
underside of its body. To achieve the specified thermal resistance, it  
must have a good thermal connection to one of the PCB planes.  
The exposed paddle must be soldered to a pad on top of the board  
that is connected with several thermal vias to a ground plane.  
Figure 48 shows how the sync signals appear on each common-  
mode voltage in a single 5 V supply application when the voltage  
applied to the SYNC LEVEL input is set to VS− + 500 mV.  
Although the typical setting for the SYNC LEVEL voltage is  
500 mV above the negative supply, it can be increased, if  
necessary, in extremely noisy environments. Increasing the  
SYNC LEVEL voltage too much has the potential to produce  
excessive EMI.  
Rev. 0 | Page 22 of 24  
 
 
 
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