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AD8142-EVALZ PDF预览

AD8142-EVALZ

更新时间: 2024-01-27 06:35:40
品牌 Logo 应用领域
亚德诺 - ADI 驱动器
页数 文件大小 规格书
24页 451K
描述
Low Cost, Triple Differential Drivers

AD8142-EVALZ 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.7
差分输出:YES驱动器位数:3
输入特性:DIFFERENTIAL接口集成电路类型:LINE DRIVER
接口标准:GENERAL PURPOSEJESD-30 代码:S-XQCC-N24
JESD-609代码:e3长度:4 mm
湿度敏感等级:1功能数量:3
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
认证状态:Not Qualified最大接收延迟:
座面最大高度:0.8 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:4 mmBase Number Matches:1

AD8142-EVALZ 数据手册

 浏览型号AD8142-EVALZ的Datasheet PDF文件第17页浏览型号AD8142-EVALZ的Datasheet PDF文件第18页浏览型号AD8142-EVALZ的Datasheet PDF文件第19页浏览型号AD8142-EVALZ的Datasheet PDF文件第21页浏览型号AD8142-EVALZ的Datasheet PDF文件第22页浏览型号AD8142-EVALZ的Datasheet PDF文件第23页 
AD8141/AD8142  
AD8142 SIGNAL LEVELS ON VARIOUS SUPPLIES  
Figure 44 and Figure 45 illustrate the key video signal levels  
seen in typical applications operating on a single +5 V supply  
and 2.5 V supplies; common-mode sync pulses are omitted  
from the circuit drawing for clarity but are shown in a separate  
waveform drawing of the signals directly at the AD8142 outputs,  
shown just below the associated circuit drawing. The sync pulses  
are common-mode, that is, they move in the same direction on  
each output polarity. In Figure 44 and Figure 45, this means that the  
HSYNC pulses are either both green or both blue for the red and  
black video signals.  
The disable pin is a binary input that controls the state of the  
AD8141/AD8142 outputs. Its binary input levels are compatible  
with most TTL and CMOS families (see Table 1 for the logic levels).  
The AD8141/AD8142output is disabled when the disable input  
is driven to its high state, and the AD8141/AD8142operates in  
its normal fashion when the disable input is driven to its low state.  
An unavoidable common-mode glitch occurs at the outputs  
when switching between disabled and enabled states and vice  
versa. The glitch lasts for a few tens of nanoseconds and is  
on the order of 2 V or 3 V. If the disable feature is used, it is  
recommended that common-mode protection be used on the  
receiver (see the AD8143 data sheet for a detailed description of  
common-mode protection)  
DISABLE FEATURE  
When asserted, the disable feature minimizes quiescent current  
consumption and provides a high-Z output. It offers a convenient  
means to connect two driver outputs together in parallel to form a  
tristate multiplexed application. The disable feature can also be  
used to minimize quiescent current drawn when a particular  
device is not being used.  
AD8142 KEY SIGNAL LEVELS ON SINGLE +5V SUPPLY  
+5V  
0.7V  
0V  
1.5V  
0.8V  
AD8142  
2kΩ  
1kΩ  
1kΩ  
49.9Ω  
49.9Ω  
75Ω  
+
100Ω  
UTP  
100Ω  
0.7V  
1.5V  
80.6Ω  
VIDEO  
SOURCE  
38.3Ω  
2kΩ  
2.2V  
1.5V  
0.76V  
0.52V  
AD8142 OUTPUT SIGNAL LEVELS INCLUDING COMMON-MODE H  
SYNC  
PULSES  
0.5V  
2.2V  
1.5V  
0.8V  
1.4V  
Figure 44. AD8142 Key Signal Levels on Single 5 V Supply; Upper Drawing Shows Schematic, and Lower Drawing Shows Output Signals with HSYNC Pulses  
Rev. 0 | Page 20 of 24  
 
 

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