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AD8142-EVALZ PDF预览

AD8142-EVALZ

更新时间: 2024-02-15 17:49:49
品牌 Logo 应用领域
亚德诺 - ADI 驱动器
页数 文件大小 规格书
24页 451K
描述
Low Cost, Triple Differential Drivers

AD8142-EVALZ 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.7
差分输出:YES驱动器位数:3
输入特性:DIFFERENTIAL接口集成电路类型:LINE DRIVER
接口标准:GENERAL PURPOSEJESD-30 代码:S-XQCC-N24
JESD-609代码:e3长度:4 mm
湿度敏感等级:1功能数量:3
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
认证状态:Not Qualified最大接收延迟:
座面最大高度:0.8 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:4 mmBase Number Matches:1

AD8142-EVALZ 数据手册

 浏览型号AD8142-EVALZ的Datasheet PDF文件第18页浏览型号AD8142-EVALZ的Datasheet PDF文件第19页浏览型号AD8142-EVALZ的Datasheet PDF文件第20页浏览型号AD8142-EVALZ的Datasheet PDF文件第22页浏览型号AD8142-EVALZ的Datasheet PDF文件第23页浏览型号AD8142-EVALZ的Datasheet PDF文件第24页 
AD8141/AD8142  
AD8142 KEY SIGNAL LEVELS ON SINGLE ±2.5V SUPPLIES  
+2.5V  
0.7V  
0V  
–1.0V  
AD8142  
2kΩ  
–1.7V  
1kΩ  
1kΩ  
49.9Ω  
49.9Ω  
75Ω  
+
100Ω  
UTP  
100Ω  
0.7V  
–1.0V  
80.6Ω  
VIDEO  
SOURCE  
38.3Ω  
2kΩ  
–0.3V  
–1.0V  
–2.5V  
–0.10V  
–0.34V  
AD8142 OUTPUT SIGNAL LEVELS INCLUDING COMMON-MODE H  
SYNC  
PULSES  
0.5V  
–0.3V  
–1.0V  
–1.7V  
1.4V  
Figure 45. AD8142 Key Signal Levels on 2.5 V Supplies; Upper Drawing Shows Schematic, and Lower Drawing Shows Output Signals with HSYNC Pulses  
horizontal sync signals as weighted sums and differences of the  
DRIVING MULTIPLE OUTPUTS  
output common-mode signals. The RGB color signals are each  
The AD8141/AD8142 can drive four parallel UTP cables (50 Ω  
transmitted differentially over separate physical channels. The  
differential load) with only 1.5% reduction in output swing (see  
fact that the differential and common-mode signals are orthogonal  
Figure 46). As is expected, driving fewer parallel cables results in  
allows the RGB color and sync signals to be separated at the  
less output swing reduction.  
channel’s receiver.  
49.9Ω  
100Ω  
49.9UTP  
Cat-5 type cable contains four balanced twisted-pair physical  
100Ω  
AD8141/AD8142  
channels that can support both differential and common-mode  
signals. Transmitting typical computer monitor video over this  
cable can be accomplished by using three of the twisted pairs for  
49.9Ω  
100Ω  
+
V
100Ω  
100Ω  
100Ω  
49.9UTP  
OCM  
the RGB and sync signals. Each color is transmitted differentially,  
one on each of the three pairs. The encoded sync signals are  
transmitted among the common-mode signals of each of the  
three pairs. To minimize EMI from the sync signals, the common-  
mode signals on each of the three pairs produced by the sync  
encoding scheme induce electric and magnetic fields that, for  
the most part, cancel each other. A conceptual block diagram  
of the sync encoding scheme is presented in Figure 47. Because  
the AD8142 has the sync encoding scheme implemented internally,  
the user simply applies the horizontal and vertical sync signals  
directly to the appropriate inputs. As described in the Theory of  
Operation section, the AD8142 accepts ground-referenced logic-  
level sync pulses (see Table 1 for the exact levels). In many cases,  
the sync pulses can be applied directly from video card VGA  
connector outputs.  
49.9Ω  
100Ω  
49.9UTP  
49.9Ω  
100Ω  
49.9UTP  
Figure 46. Driving Four UTP Cables in Parallel  
VIDEO SYNC-ON-COMMON-MODE (AD8142)  
In computer video applications, the horizontal and vertical sync  
signals are most often separate from the video information signals.  
For example, in typical computer monitor applications, the red,  
green, and blue (RGB) color signals are transmitted over separate  
cables, as are the vertical and horizontal sync signals. When  
transmitting these types of video signals over long distances  
on UTP cable, it is desirable to reduce the required number of  
physical channels. One way to do this is to encode the vertical and  
Rev. 0 | Page 21 of 24  
 
 
 

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