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AD73560BB-40 PDF预览

AD73560BB-40

更新时间: 2024-01-08 04:59:34
品牌 Logo 应用领域
亚德诺 - ADI 时钟外围集成电路
页数 文件大小 规格书
39页 641K
描述
IC 0-BIT, 16.384 MHz, OTHER DSP, PBGA119, PLASTIC, BGA-119, Digital Signal Processor

AD73560BB-40 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:PLASTIC, BGA-119
针数:119Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.92地址总线宽度:
桶式移位器:YES位大小:16
边界扫描:NO最大时钟频率:16.384 MHz
外部数据总线宽度:格式:FIXED POINT
内部总线架构:MULTIPLEJESD-30 代码:R-PBGA-B119
JESD-609代码:e0长度:22 mm
低功率模式:YES端子数量:119
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA119,7X17,50封装形状:RECTANGULAR
封装形式:GRID ARRAY峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
RAM(字数):8192座面最大高度:2.27 mm
子类别:Digital Signal Processors最大供电电压:3.3 V
最小供电电压:2.7 V标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

AD73560BB-40 数据手册

 浏览型号AD73560BB-40的Datasheet PDF文件第30页浏览型号AD73560BB-40的Datasheet PDF文件第31页浏览型号AD73560BB-40的Datasheet PDF文件第32页浏览型号AD73560BB-40的Datasheet PDF文件第34页浏览型号AD73560BB-40的Datasheet PDF文件第35页浏览型号AD73560BB-40的Datasheet PDF文件第36页 
Preliminary Technical Data  
AD73560  
Flash-Erase operation is initiated by using a specific six  
byte-load sequence. After the load sequence, the device  
enters into an internally timed cycle similar to the write  
cycle. During the erase operation, the only valid read is  
T oggle Bit. See Figure 27 for timing diagram.  
Softwa r e C h ip - E r a se  
T he AD73560 provides a flash-erase operation, which  
allows the user to simultaneously clear the entire flash-  
memory array to the “1” state. T his is useful when the  
entire flash memory must be quickly erased. T he Software  
T
T
RC  
AA  
ADDRESS A  
15-0  
T
CE  
T
CE (BM S )  
O E (R D)  
OE  
T
OHZ  
T
V
OLZ  
IH  
W E (W R)  
T
CHZ  
T
T
O H  
CLZ  
High-Z  
DATA VALID  
DATA VALID  
DB  
7-0  
Figure 21. Read Cycle Tim ing  
THREE BYTE SEQUENCE  
FOR ENABLING SDP  
T
AH  
T
AS  
ADDRESS A  
5555  
2AAA  
5555  
15-0  
T
T
CH  
CS  
CE (BM S)  
T
T
OEH  
OES  
O E (R D)  
W E (W R)  
T
WP  
T
T
BLC  
BLCO  
T
DH  
DB  
7-0  
DATA VALID  
AA  
A0  
55  
T
SW0  
SW2  
WC  
SW1  
T
DS  
BYTE 127  
BYTE 1  
BYTE 0  
Figure 22. WR Controlled Page Mode Write Cycle Tim ing  
REV. PrA  
–3 3 –  

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