5秒后页面跳转
AD73322EZ PDF预览

AD73322EZ

更新时间: 2024-02-29 03:20:49
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
43页 389K
描述
Low Cost Low Power CMOS General-Purpose Dual Analog Front End(386.88 k)

AD73322EZ 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:44
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.58
Is Samacsys:NJESD-30 代码:S-PQFP-G44
JESD-609代码:e3长度:14 mm
湿度敏感等级:3功能数量:1
端子数量:44最高工作温度:105 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.6 mm
标称供电电压:3 V表面贴装:YES
技术:CMOS电信集成电路类型:TELECOM CIRCUIT
温度等级:INDUSTRIAL端子面层:Tin (Sn)
端子形式:GULL WING端子节距:1 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

AD73322EZ 数据手册

 浏览型号AD73322EZ的Datasheet PDF文件第6页浏览型号AD73322EZ的Datasheet PDF文件第7页浏览型号AD73322EZ的Datasheet PDF文件第8页浏览型号AD73322EZ的Datasheet PDF文件第10页浏览型号AD73322EZ的Datasheet PDF文件第11页浏览型号AD73322EZ的Datasheet PDF文件第12页 
AD73322  
(AVDD = +5 V ؎ 10%; DVDD = +5 V ؎ 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless  
otherwise noted)  
TIMING CHARACTERISTICS  
Limit at  
Parameter  
TA = –40؇C to +85؇C  
Units  
Description  
Clock Signals  
See Figure 1  
t1  
t2  
t3  
61  
24.4  
24.4  
ns min  
ns min  
ns min  
MCLK Period  
MCLK Width High  
MCLK Width Low  
Serial Port  
See Figures 3 and 4  
t4  
t5  
t6  
t7  
t8  
t9  
t10  
t11  
t12  
t13  
t1  
ns min  
ns min  
ns min  
ns typ  
ns typ  
ns typ  
ns typ  
ns typ  
ns typ  
ns typ  
SCLK Period  
SCLK Width High  
SCLK Width Low  
SDI/SDIFS Setup Before SCLK Low  
SDI/SDIFS Hold After SCLK Low  
SDOFS Delay from SCLK High  
SDOFS Hold After SCLK High  
SDO Hold After SCLK High  
SDO Delay from SCLK High  
SCLK Delay from MCLK  
0.4 × t1  
0.4 × t1  
20  
0
10  
10  
10  
10  
30  
Specifications subject to change without notice.  
t1  
100A  
I
OL  
t2  
TO OUTPUT  
PIN  
+2.1V  
C
L
15pF  
I
100A  
OH  
t3  
Figure 1. MCLK Timing  
Figure 2. Load Circuit for Timing Specifications  
t2  
t1  
t3  
MCLK  
SCLK*  
t13  
t6  
t5  
t4  
* SCLK IS INDIVIDUALLY PROGRAMMABLE  
IN FREQUENCY (MCLK/4 SHOWN HERE).  
Figure 3. SCLK Timing  
SE (I)  
THREE-  
STATE  
SCLK (O)  
SDIFS (I)  
t7  
t8  
t8  
t7  
SDI (I)  
D15  
D14  
D1  
D0  
D15  
t10  
THREE-  
STATE  
t9  
SDOFS (O)  
t12  
t11  
THREE-  
STATE  
SDO (O)  
D15  
D2  
D1  
D0  
D15  
D14  
Figure 4. Serial Port (SPORT)  
–9–  
REV. B  

与AD73322EZ相关器件

型号 品牌 获取价格 描述 数据表
AD73322L ADI

获取价格

Low Cost, Low Power CMOS General-Purpose Dual Analog Front End
AD73322L_17 ADI

获取价格

Low Cost, Low Power CMOS General-Purpose Dual Analog Front
AD73322LAR ADI

获取价格

Low Cost, Low Power CMOS General-Purpose Dual Analog Front End
AD73322LAR-REEL ADI

获取价格

暂无描述
AD73322LAR-REEL7 ADI

获取价格

IC SPECIALTY TELECOM CIRCUIT, PDSO28, MS-013AE, SOIC-28, Telecom IC:Other
AD73322LARU ADI

获取价格

Low Cost, Low Power CMOS General-Purpose Dual Analog Front End
AD73322LARU-REEL ADI

获取价格

IC SPECIALTY TELECOM CIRCUIT, PDSO28, MO-153AE, TSSOP-28, Telecom IC:Other
AD73322LARUZ ADI

获取价格

Dual-Channel, 3 V Front-End Processor for General Purpose Applications Including Speech an
AD73322LARUZ1 ADI

获取价格

Low Cost, Low Power CMOS General-Purpose Dual Analog Front
AD73322LARUZ-REEL ADI

获取价格

SPECIALTY TELECOM CIRCUIT, PDSO28, LEAD FREE, MO-153AE, TSSOP-28