AD73322AST-REEL

更新时间： 2024-01-26 12:29:59

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
43页	389K
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数据手册

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AD73322AST-REEL 数据手册

(AVDD = +3 V ؎ 10%; DVDD = +3 V ؎ 10%; DGND = AGND = 0 V, f_DMCLK

16.384 MHz, f_SAMP= 64 kHz; T_A= T_MINto T_MAX, unless otherwise noted)

AD73322–SPECIFICATIONS¹

AD73322A

Parameter

Min

Typ

Max

Units

Test Conditions/Comments

REFERENCE

REFCAP

5VEN = 0

Absolute Voltage, VREFCAP

REFCAP TC

1.08

1.2

1.32

ppm/°C 0.1 µF Capacitor Required from

REFOUT

REFCAP to AGND2

Typical Output Impedance

Absolute Voltage, V_REFOUT

Minimum Load Resistance

Maximum Load Capacitance

130

1.2

Ω

kΩ

1.08

1.32

100

Unloaded

INPUT AMPLIFIER

Offset

Maximum Output Swing

Feedback Resistance

Feedback Capacitance

±1.0

1.578

Ω

Max Output Swing = (1.578/1.2) × VREFCAP

f_C= 32 kHz

100

ANALOG GAIN TAP

Gain at Maximum Setting

Gain at Minimum Setting

Gain Resolution

Gain Accuracy

Settling Time

–1

±1.0

1.0

0.5

Bits

µs

Gain Step Size = 0.0625

Output Unloaded

Tap Gain Change of –FS to +FS

Delay

µs

ADC SPECIFICATIONS

5VEN = 0

Maximum Input Range at VIN^{2, 3}

1.578

–2.85

1.0954

–6.02

V p-p

dBm

V p-p

dBm

Measured Differentially

Max Input = (1.578/1.2) × VREFCAP

Measured Differentially

Nominal Reference Level at VIN

(0 dBm0)

Absolute Gain

PGA = 0 dB

PGA = 38 dB

Gain Tracking Error

Signal to (Noise + Distortion)

PGA = 0 dB

–0.5

–1.5

0.4

–0.7

±0.1

+1.2

+0.1

1.0 kHz, 0 dBm0

1.0 kHz, +3 dBm0 to –50 dBm0

Refer to Figure 5

300 Hz to 3400 Hz; f_SAMP= 64 kHz

300 Hz to 3400 Hz; f_SAMP= 8 kHz

0 Hz to f_SAMP/2; f_SAMP= 64 kHz

300 Hz to 3400 Hz; f_SAMP= 64 kHz

PGA = 38 dB

Total Harmonic Distortion

PGA = 0 dB

PGA = 38 dB

Intermodulation Distortion

Idle Channel Noise

–84

–70

–65

–71

–100

–73

–60

dBm0

300 Hz to 3400 Hz; f_SAMP= 64 kHz

PGA = 0 dB

ADC Input Signal Level: 1.0 kHz, 0 dBm0

DAC Input at Idle

Crosstalk

ADC-to-DAC

ADC-to-ADC

–100

ADC1 Input Signal Level: 1.0 kHz, 0 dBm0

ADC2 Input at Idle. Input Amplifiers Bypassed

Input Amplifiers Included in Input Channel

PGA = 0 dB

Input Signal Level at AVDD and DVDD

Pins: 1.0 kHz, 100 mV p-p Sine Wave

–70

+10

–65

DC Offset

–30

+45

Power Supply Rejection

Group Delay^{4, 5}

µs

kΩ

Input Resistance at PGA^{2, 4, 6}

Input Amplifiers Bypassed

DIGITAL GAIN TAP

Gain at Maximum Setting

Gain at Minimum Setting

Gain Resolution

–1

Bits

µs

Tested to 5 MSBs of Settings

Includes DAC Delay

Delay

Settling Time

100

µs

Tap Gain Change from –FS to +FS; Includes

DAC Settling Time

–2–

REV. B

123 4 5 6 7...43

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