AD73322
AD73322A
Typ
P
arameter
Min
Max
Units
Test Conditions/Comments
DIGITAL GAIN TAP
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Delay
Settling Time
+1
–1
16
25
100
V
V
Bits
µs
µs
Tested to 5 MSBs of Settings
Includes DAC Delay
Tap Gain Change from –FS to +FS; Includes
DAC Settling Time
DAC SPECIFICATIONS
Maximum Voltage Output Swing2
Single-Ended
5VEN = 1
3.156
3.17
6.312
9.19
V p-p
dBm
V p-p
dBm
PGA = 6 dB
Max Output = (3.156/2.4) × VREFCAP
PGA = 6 dB
Differential
Max Output = 2 × ([3.156/2.4] × VREFCAP)
Nominal Voltage Output Swing (0 dBm0)
Single-Ended
2.1908
0
4.3918
6.02
2.4
V p-p
dBm
V p-p
dBm
V
PGA = 6 dB
PGA = 6 dB
Differential
Output Bias Voltage
REFOUT Unloaded
Absolute Gain
Gain Tracking Error
Signal to (Noise + Distortion) at 0 dBm0
PGA = 6 dB
+0.4
±0.1
dB
dB
1.0 kHz, 0 dBm0; Unloaded
1.0 kHz, +3 dBm0 to –50 dBm0
Refer to Figure 8
77
dB
300 Hz to 3400 Hz; fSAMP = 64 kHz
Total Harmonic Distortion at 0 dBm0
PGA = 6 dB
Intermodulation Distortion
Idle Channel Noise
–80
–85
–85
–90
dB
dB
dBm0
dB
300 Hz to 3400 Hz; fSAMP = 64 kHz
PGA = 0 dB
PGA = 0 dB
ADC Input Signal Level: AGND; DAC
Output Signal Level: 1.0 kHz, 0 dBm0;
Input Amplifiers Bypassed
Crosstalk DAC-to-ADC
–77
–100
dB
dB
Input Amplifiers Included In Input Channel
DAC1 Output Signal Level: AGND; DAC2
Output Signal Level: 1.0 kHz, 0 dBm0
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
Interpolator Bypassed
DAC-to-DAC
Power Supply Rejection
Group Delay4, 5
–65
dB
25
µs
50
+12
µs
mV
Output DC Offset2, 7
Minimum Load Resistance, RL
2, 8
Single-Ended
Differential
Maximum Load Capacitance, CL
150
150
Ω
Ω
2, 8
Single-Ended
Differential
500
100
pF
pF
FREQUENCY RESPONSE
(ADC and DAC)9 Typical Output
Frequency (Normalized to FS)
0
0
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
0.03125
0.0625
0.125
0.1875
0.25
0.3125
0.375
0.4375
> 0.5
–0.1
–0.25
–0.6
–1.4
–2.8
–4.5
–7.0
–9.5
< –12.5
–6–
REV. B