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AD7304BR-REEL7

更新时间： 2024-02-07 19:42:29
品牌 Logo 应用领域
亚德诺 - ADI 输入元件光电二极管转换器
页数 文件大小 规格书
20页 895K
描述
IC SERIAL INPUT LOADING, 1 us SETTLING TIME, 8-BIT DAC, PDSO16, MS-013AA, SOIC-16, Digital to Analog Converter

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AD7304BR-REEL7 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：MS-013AA, SOIC-16
针数：16Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.25Is Samacsys：N
最大模拟输出电压：5 V最小模拟输出电压：-5 V
转换器类型：D/A CONVERTER输入位码：BINARY
输入格式：SERIALJESD-30 代码：R-PDSO-G16
JESD-609代码：e0长度：10.3 mm
最大线性误差 (EL)：0.3906%湿度敏感等级：1
标称负供电电压：-5 V位数：8
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3/5 V认证状态：Not Qualified
座面最大高度：2.65 mm最大稳定时间：0.2 µs
标称安定时间 (tstl)：1 µs子类别：Other Converters
最大压摆率：6 mA标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmBase Number Matches：1

AD7304BR-REEL7 数据手册

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3 V/5 V, Rail-to-Rail  
Quad, 8-Bit DAC  
AD7304/AD7305  
FUNCTIONAL BLOCK DIAGRAMS  
FEATURES  
Four 8-bit DACs in one package  
V
B
V
A
V
REF  
REF  
DD  
+3 V, +5 V, and 5 V operation  
8
8
8
8
8
PWR-ON  
RESET  
INPUT  
REG A  
DAC A  
REG  
V
V
V
V
A
B
C
D
DAC A  
DAC B  
DAC C  
DAC D  
Rail-to-rail REF input to voltage output swing  
2.6 MHz reference multiplying bandwidth  
Internal power-on reset  
SPI serial interface-compatible—AD7304  
Fast parallel interface—AD7305  
40 µA power shutdown  
OUT  
8
8
8
8
INPUT  
REG B  
DAC B  
REG  
OUT  
CS  
INPUT  
REG C  
DAC C  
REG  
OUT  
OUT  
SERIAL  
REG  
SDI/SHDN  
CLK  
INPUT  
REG D  
DAC D  
REG  
APPLICATIONS  
Automotive output span voltage  
Instrumentation, digitally controlled calibration  
Pin-compatible AD7226 replacement when VDD < 5.5 V  
AD7304  
V
GND  
V
C V  
D
REF  
SS  
REF  
CLR LDAC  
Figure 1.  
V
8
V
REF  
DD  
GENERAL DESCRIPTION  
8
PWR-ON  
RESET  
INPUT  
REG A  
DAC A  
The AD7304/AD73051 are quad, 8-bit DACs that operate from  
a single +3 V to +5 V supply, or 5 V supplies. The AD7304 has  
a serial interface, while the AD7305 has a parallel interface.  
Internal precision buffers swing rail-to-rail. The reference input  
range includes both supply rails, allowing for positive or negative  
full-scale output voltages. Operation is guaranteed over the  
supply voltage range of 2.7 V to 5.5 V, consuming less than  
9 mW from a 3 V supply.  
V
V
A
DAC A  
DAC B  
DAC C  
DAC D  
OUT  
REG  
DB0  
DB1  
DB2  
DB3  
DB4  
DB5  
DB6  
8
8
8
8
8
INPUT  
REG B  
DAC B  
B
OUT  
REG  
8
INPUT  
REG C  
DAC C  
V
V
C
D
OUT  
OUT  
REG  
8
8
INPUT  
REG D  
DAC D  
REG  
WR  
A0/SHDN  
A1  
DECODE  
AD7305  
V
SS  
GND  
LDAC  
The full-scale voltage output is determined by the external  
reference input voltage applied. The rail-to-rail VREF input to  
DAC VOUT allows for a full-scale voltage set equal to the positive  
supply, VDD, the negative supply, VSS, or any value in between.  
Figure 2.  
When operating from less than 5.5 V, the AD7305 is  
pin-compatible with the popular industry-standard AD7226.  
The AD7304’s doubled-buffered serial data interface offers high  
speed, 3-wire, SPI®-, and microcontroller-compatible inputs  
An internal power-on reset places both parts in the zero-scale  
state at turn-on. A 40 µA power shutdown (SHDN) feature is  
activated on both parts by three-stating the SDI/SHDN pin on  
the AD7304 and three-stating the A0/SHDN address pin on the  
AD7305.  
CS  
using data in (SDI), clock (CLK), and chip select ( ) pins.  
Additionally, an internal power-on reset sets the output to zero  
scale.  
The parallel input AD7305 uses a standard address decode  
The AD7304/AD7305 are specified over the extended industrial  
−40°C to +85°C and the automotive −40°C to +125°C  
temperature ranges. AD7304s are available in a wide-body  
16-lead SOIC (R-16) package. The parallel input AD7305 is  
available in the wide-body 20-lead SOIC (R-20) surface-mount  
package. For ultracompact applications, the thin 1.1 mm,  
16-lead TSSOP (RU-16) package is available for the AD7304,  
while the 20-lead TSSOP (RU-20) houses the AD7305.  
WR  
along with the  
registers.  
control line to load data into the input  
The double-buffered architecture allows all four input registers  
LDAC  
to be preloaded with new values, followed by an  
control  
strobe that copies all the new data into the DAC registers,  
thereby updating the analog output values.  
_____________________________________________________  
1 Protected under Patent No. 5684481.  
Rev. C  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  
 
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